On Thu, 2022-10-27 at 10:21 +0200, AngeloGioacchino Del Regno wrote:
> Il 24/10/22 11:42, Garmin.Chang ha scritto:
> > Add MT8188 apmixedsys clock controller which provides Plls
> > generated from SoC 26m and ssusb clock gate control.
> >
> > Signed-off-by: Garmin.Chang <Garmin.Chang@xxxxxxxxxxxx>
> > Change-Id: I3b1b44155cc5bfe5ba6e860de857e7e9f48b66a7
> > ---
> > drivers/clk/mediatek/Kconfig | 11 ++
> > drivers/clk/mediatek/Makefile | 1 +
> > drivers/clk/mediatek/clk-mt8188-apmixedsys.c | 153
> > +++++++++++++++++++
> > 3 files changed, 165 insertions(+)
> > create mode 100644 drivers/clk/mediatek/clk-mt8188-apmixedsys.c
> >
>
> ..snip..
>
> > diff --git a/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
> > b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
> > new file mode 100644
> > index 000000000000..f09e11d0261e
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8188-apmixedsys.c
>
> ..snip..
>
> > +
> > +static int clk_mt8188_apmixed_probe(struct platform_device *pdev)
> > +{
> > + struct clk_hw_onecell_data *clk_data;
> > + struct device_node *node = pdev->dev.of_node;
> > + int r;
> > +
> > + clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
> > + if (!clk_data)
> > + return -ENOMEM;
> > +
> > + r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls),
> > clk_data);
> > + if (r)
> > + goto free_apmixed_data;
> > +
> > + r = mtk_clk_register_gates(node, apmixed_clks,
> > ARRAY_SIZE(apmixed_clks), clk_data);
>
> Please use mtk_clk_register_gates_with_dev().
>
> Regards,
> Angelo
Ok, I will use mtk_clk_register_gates_with_dev() in the next version.
> Thanks,
> Best Regards,
> Garmin
