On Thu, 2022-10-27 at 10:23 +0200, AngeloGioacchino Del Regno wrote:
> Il 24/10/22 11:42, Garmin.Chang ha scritto:
> > Add MT8188 mfg clock controller which provides clock gate
> > control for GPU.
> >
> > Signed-off-by: Garmin.Chang <Garmin.Chang@xxxxxxxxxxxx>
> > ---
> > drivers/clk/mediatek/Makefile | 2 +-
> > drivers/clk/mediatek/clk-mt8188-mfg.c | 50
> > +++++++++++++++++++++++++++
> > 2 files changed, 51 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/clk/mediatek/clk-mt8188-mfg.c
> >
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index 21b05e880a3a..cd8870c28146 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -85,7 +85,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-
> > mcu.o clk-mt8186-topckgen.o clk-mt
> > obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-
> > mt8188-topckgen.o \
> > clk-mt8188-peri_ao.o clk-mt8188-
> > infra_ao.o \
> > clk-mt8188-cam.o clk-mt8188-ccu.o
> > clk-mt8188-img.o \
> > - clk-mt8188-ipe.o
> > + clk-mt8188-ipe.o clk-mt8188-mfg.o
> > obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > diff --git a/drivers/clk/mediatek/clk-mt8188-mfg.c
> > b/drivers/clk/mediatek/clk-mt8188-mfg.c
> > new file mode 100644
> > index 000000000000..3a75cd7443fd
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8188-mfg.c
> > @@ -0,0 +1,50 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2022 MediaTek Inc.
> > +// Author: Garmin Chang <garmin.chang@xxxxxxxxxxxx>
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > +
> > +#include "clk-gate.h"
> > +#include "clk-mtk.h"
> > +
> > +static const struct mtk_gate_regs mfgcfg_cg_regs = {
> > + .set_ofs = 0x4,
> > + .clr_ofs = 0x8,
> > + .sta_ofs = 0x0,
> > +};
> > +
> > +#define GATE_MFGCFG(_id, _name, _parent, _shift)
> > \
> > + GATE_MTK(_id, _name, _parent, &mfgcfg_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr)
> > +
> > +static const struct mtk_gate mfgcfg_clks[] = {
> > + GATE_MFGCFG(CLK_MFGCFG_BG3D, "mfgcfg_bg3d", "top_mfg_core_tmp",
> > 0),
> > +};
>
> This will make it impossible to properly perform GPU DVFS.
>
> Hint:
>
> #define GATE_MFG(_id, _name, _parent, _shift) \
> GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, \
> _shift, &mtk_clk_gate_ops_setclr, \
> CLK_SET_RATE_PARENT)
>
> Regards,
> Angelo
>
Ok, I will modify them in the next version.
>
> Thanks,
> Best Regards,
> Garmin
