Re: [PATCH v4 2/4] arm64: dts: qcom: sm6125: Add UFS nodes

[Lux Aliaga <they@xxxxxxxxx>]

On 16/12/2022 08:24, Konrad Dybcio wrote:
> On 15.12.2022 20:04, Lux Aliaga wrote:
> > Adds a UFS host controller node and its corresponding PHY to
> > the sm6125 platform.
> >
> > Signed-off-by: Lux Aliaga <they@xxxxxxxxx>
> > ---
> Please include a changelog, I don't know what you changed and
> what you didn't. Also, you sent 4 revisions in one day, not
> letting others review it.
>
>
> >   arch/arm64/boot/dts/qcom/sm6125.dtsi | 67 ++++++++++++++++++++++++++++
> >   1 file changed, 67 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> > index 7e25a4f85594..b64c5bc1452f 100644
> > --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
> > @@ -508,6 +508,73 @@ sdhc_2: mmc@4784000 {
> >   			status = "disabled";
> >   		};
> >   
> > +		ufs_mem_hc: ufs@4804000 {
> > +			compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
> > +			reg = <0x04804000 0x3000>, <0x04810000 0x8000>;
> > +			reg-names = "std", "ice";
> > +			interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
> > +			phys = <&ufs_mem_phy_lanes>;
> > +			phy-names = "ufsphy";
> > +			lanes-per-direction = <1>;
> > +			#reset-cells = <1>;
> > +			resets = <&gcc GCC_UFS_PHY_BCR>;
> > +			reset-names = "rst";
> > +
> > +			clock-names = "core_clk",
> > +				      "bus_aggr_clk",
> > +				      "iface_clk",
> > +				      "core_clk_unipro",
> > +				      "ref_clk",
> > +				      "tx_lane0_sync_clk",
> > +				      "rx_lane0_sync_clk",
> > +				      "ice_core_clk";
> > +			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
> > +				 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
> > +				 <&gcc GCC_UFS_PHY_AHB_CLK>,
> > +				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> > +				 <&rpmcc RPM_SMD_XO_CLK_SRC>,
> > +				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> > +				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> > +				 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
> > +			freq-table-hz = <50000000 240000000>,
> > +					<0 0>,
> > +					<0 0>,
> > +					<37500000 150000000>,
> > +					<0 0>,
> > +					<0 0>,
> > +					<0 0>,
> > +					<75000000 300000000>;
> > +
> > +			non-removable;
> > +			status = "disabled";
> > +		};
> > +
> > +		ufs_mem_phy: phy@4807000 {
> > +			compatible = "qcom,sm6115-qmp-ufs-phy";
> Krzysztof asked you to add a SoC-specific compatible in v1.
>
>
> > +			reg = <0x04807000 0x1c4>;
> > +
> > +			power-domains = <&gcc UFS_PHY_GDSC>;
> > +
> > +			clock-names = "ref", "ref_aux";
> > +			clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
> > +
> > +			resets = <&ufs_mem_hc 0>;
> > +			reset-names = "ufsphy";
> > +
> > +			#address-cells = <1>;
> > +			#size-cells = <1>;
> > +			ranges;
> > +
> > +			status = "disabled";
> > +
> > +			ufs_mem_phy_lanes: lanes@4807400 {
> > +				reg = <0x4807400 0x098>,
> > +				      <0x4807600 0x130>,
> > +				      <0x4807c00 0x16c>;
> > +				#phy-cells = <0>;
> > +			};
> I believe this is deprecated. See [1].
>
>
> Konrad
>
> [1] https://lore.kernel.org/linux-arm-msm/20221104092045.17410-1-johan+linaro@xxxxxxxxxx/T/#m988f3fe3d83b76bac247aea2d9dac34f37728d65
I've looked into the documentation and this is only for the sc8280xp. 
This PHY is defined as it is for the msm8996 and derivatives.

--
Lux Aliaga
https://nixgoat.me/