Hi Conor, On Mon, Dec 19, 2022 at 4:20 PM Conor Dooley <conor@xxxxxxxxxx> wrote: > > On Mon, Dec 19, 2022 at 11:19:13AM +0000, Lad, Prabhakar wrote: > > Hi Conor, > > > > Thank you for the review. > > > > On Sat, Dec 17, 2022 at 9:19 PM Conor Dooley <conor@xxxxxxxxxx> wrote: > > > > > > On Mon, Dec 12, 2022 at 11:55:02AM +0000, Prabhakar wrote: > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > > > > > > > Add required ports of the Alternative scheme for Andes CPU cores. > > > > > > > > I/O Coherence Port (IOCP) provides an AXI interface for connecting external > > > > non-caching masters, such as DMA controllers. IOCP is a specification > > > > option and is disabled on the Renesas RZ/Five SoC due to this reason cache > > > > management needs a software workaround. > > > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > > > --- > > > > v4 -> v5 > > > > * Sorted the Kconfig/Makefile/Switch based on Core name > > > > * Added a comments > > > > * Introduced RZFIVE_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT ID to check if > > > > CMO needs to be applied. Is there a way we can access the DTB while patching > > > > as we can drop this SBI EXT ID and add a DT property instead for cmo? > > > > <snip> > > > Seeing as you need a new version for some of the other bits, I think it > > > would be good to add a minor comment here somewhere (be it here or the > > > commit message) that links to the SBI specs for this. > > > I think this looks pretty good though. > > Sure I'll add a comment here. > > > > I was wondering if we can get rid of this vendor specific extension > > here if we get access to the DT here (for example having a DT property > > which would indicate if IOCP CMO should be applied or not). Do you > > think that would be good approach? ATM we dont have a pointer here > > for FDT whie early patching. > > I dunno. I think it is fine to use the ECALL to be honest - I'd rather > that than a property that someone may omit. > Ok, I was so I will stick with the current implementation. > That said, for the cache management stuff we are gonna need for > PolarFire SoC, we will need to have info from the DT AFAICT - marchid > etc are all set to zero on our platform so cannot be used. > Aha so while patching you will need a pointer to FDT node. > I was thinking about using the compatible instead, but... > we've not tried to "forward"-port our stuff from 5.15 yet as we have > not yet completed testing testing on our vendor tree (and need some PCI > changes accepted upstream first anyway), as a result I have not looked > into what's needed there for use with alternatives. We've been using a > pre-alternatives version of that patchset from around the 5.15 > development point in time instead. > Good to know. Let me know if you plan to implement the patching mechanism based on FDT soon. I can give it a test. Cheers, Prabhakar
