On Tue, 20 Dec 2022 08:50:51 +0800, Hal Feng wrote: > From: Emil Renner Berthing <kernel@xxxxxxxx> > > Add bindings for the always-on clock and reset generator (AONCRG) on the > JH7110 RISC-V SoC by StarFive Ltd. > > Signed-off-by: Emil Renner Berthing <kernel@xxxxxxxx> > Signed-off-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx> > --- > .../clock/starfive,jh7110-aoncrg.yaml | 76 +++++++++++++++++++ > .../dt-bindings/clock/starfive,jh7110-crg.h | 18 +++++ > .../dt-bindings/reset/starfive,jh7110-crg.h | 12 +++ > 3 files changed, 106 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml > Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
