On 20.12.2022 03:47, Dmitry Baryshkov wrote:
> Specify pre-parsed per-sensor calibration nvmem cells in the tsens
> device node rather than parsing the whole data blob in the driver.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/qcs404.dtsi | 121 +++++++++++++++++++++++++--
> 1 file changed, 116 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> index a5324eecb50a..362764347006 100644
> --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> @@ -366,13 +366,102 @@ qfprom: qfprom@a4000 {
> reg = <0x000a4000 0x1000>;
> #address-cells = <1>;
> #size-cells = <1>;
> - tsens_caldata: caldata@d0 {
> - reg = <0x1f8 0x14>;
> - };
> cpr_efuse_speedbin: speedbin@13c {
> reg = <0x13c 0x4>;
> bits = <2 3>;
> };
Oh wow, this list is even longer.. can you pinky-promise it's
correct? :P In any case, please add newlines between each
subnode and rename the nodes so that there aren't underscores
in the node names.
Konrad
> + tsens_s0_p1: s0_p1@1f8 {
> + reg = <0x1f8 0x1>;
> + bits = <0 6>;
> + };
> + tsens_s0_p2: s0_p2@1f8 {
> + reg = <0x1f8 0x2>;
> + bits = <6 6>;
> + };
> + tsens_s1_p1: s1_p1@1f9 {
> + reg = <0x1f9 0x2>;
> + bits = <4 6>;
> + };
> + tsens_s1_p2: s1_p2@1fa {
> + reg = <0x1fa 0x1>;
> + bits = <2 6>;
> + };
> + tsens_s2_p1: s2_p1@1fb {
> + reg = <0x1fb 0x1>;
> + bits = <0 6>;
> + };
> + tsens_s2_p2: s2_p2@1fb {
> + reg = <0x1fb 0x2>;
> + bits = <6 6>;
> + };
> + tsens_s3_p1: s3_p1@1fc {
> + reg = <0x1fc 0x2>;
> + bits = <4 6>;
> + };
> + tsens_s3_p2: s3_p2@1fd {
> + reg = <0x1fd 0x1>;
> + bits = <2 6>;
> + };
> + tsens_s4_p1: s4_p1@1fe {
> + reg = <0x1fe 0x1>;
> + bits = <0 6>;
> + };
> + tsens_s4_p2: s4_p2@1fe {
> + reg = <0x1fe 0x2>;
> + bits = <6 6>;
> + };
> + tsens_s5_p1: s5_p1@200 {
> + reg = <0x200 0x1>;
> + bits = <0 6>;
> + };
> + tsens_s5_p2: s5_p2@200 {
> + reg = <0x200 0x2>;
> + bits = <6 6>;
> + };
> + tsens_s6_p1: s6_p1@201 {
> + reg = <0x201 0x2>;
> + bits = <4 6>;
> + };
> + tsens_s6_p2: s6_p2@202 {
> + reg = <0x202 0x1>;
> + bits = <2 6>;
> + };
> + tsens_s7_p1: s7_p1@203 {
> + reg = <0x203 0x1>;
> + bits = <0 6>;
> + };
> + tsens_s7_p2: s7_p2@203 {
> + reg = <0x203 0x2>;
> + bits = <6 6>;
> + };
> + tsens_s8_p1: s8_p1@204 {
> + reg = <0x204 0x2>;
> + bits = <4 6>;
> + };
> + tsens_s8_p2: s8_p2@205 {
> + reg = <0x205 0x1>;
> + bits = <2 6>;
> + };
> + tsens_s9_p1: s9_p1@206 {
> + reg = <0x206 0x1>;
> + bits = <0 6>;
> + };
> + tsens_s9_p2: s9_p2@206 {
> + reg = <0x206 0x2>;
> + bits = <6 6>;
> + };
> + tsens_mode: mode@208 {
> + reg = <0x208 1>;
> + bits = <0 3>;
> + };
> + tsens_base1: base1@208 {
> + reg = <0x208 2>;
> + bits = <3 8>;
> + };
> + tsens_base2: base2@208 {
> + reg = <0x209 2>;
> + bits = <3 8>;
> + };
> cpr_efuse_quot_offset1: qoffset1@231 {
> reg = <0x231 0x4>;
> bits = <4 7>;
> @@ -447,8 +536,30 @@ tsens: thermal-sensor@4a9000 {
> compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
> reg = <0x004a9000 0x1000>, /* TM */
> <0x004a8000 0x1000>; /* SROT */
> - nvmem-cells = <&tsens_caldata>;
> - nvmem-cell-names = "calib";
> + nvmem-cells = <&tsens_mode>,
> + <&tsens_base1>, <&tsens_base2>,
> + <&tsens_s0_p1>, <&tsens_s0_p2>,
> + <&tsens_s1_p1>, <&tsens_s1_p2>,
> + <&tsens_s2_p1>, <&tsens_s2_p2>,
> + <&tsens_s3_p1>, <&tsens_s3_p2>,
> + <&tsens_s4_p1>, <&tsens_s4_p2>,
> + <&tsens_s5_p1>, <&tsens_s5_p2>,
> + <&tsens_s6_p1>, <&tsens_s6_p2>,
> + <&tsens_s7_p1>, <&tsens_s7_p2>,
> + <&tsens_s8_p1>, <&tsens_s8_p2>,
> + <&tsens_s9_p1>, <&tsens_s9_p2>;
> + nvmem-cell-names = "mode",
> + "base1", "base2",
> + "s0_p1", "s0_p2",
> + "s1_p1", "s1_p2",
> + "s2_p1", "s2_p2",
> + "s3_p1", "s3_p2",
> + "s4_p1", "s4_p2",
> + "s5_p1", "s5_p2",
> + "s6_p1", "s6_p2",
> + "s7_p1", "s7_p2",
> + "s8_p1", "s8_p2",
> + "s9_p1", "s9_p2";
> #qcom,sensors = <10>;
> interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "uplow";
