Hi Lucas: > -----Original Message----- > From: Lucas Stach <l.stach@xxxxxxxxxxxxxx> > Sent: 2022年12月16日 1:50 > To: Rob Herring <robh+dt@xxxxxxxxxx>; Krzysztof Kozlowski > <krzysztof.kozlowski+dt@xxxxxxxxxx>; Shawn Guo <shawnguo@xxxxxxxxxx>; > Hongxing Zhu <hongxing.zhu@xxxxxxx> > Cc: dl-linux-imx <linux-imx@xxxxxxx>; Pengutronix Kernel Team > <kernel@xxxxxxxxxxxxxx>; Marcel Ziswiler <marcel.ziswiler@xxxxxxxxxxx>; > marex@xxxxxxx; tharvey@xxxxxxxxxxxxx; alexander.stein@xxxxxxxxxxxxxxx; > richard.leitner@xxxxxxxxx; lukas@xxxxxxxxx; patchwork-lst@xxxxxxxxxxxxxx; > devicetree@xxxxxxxxxxxxxxx; linux-arm-kernel@xxxxxxxxxxxxxxxxxxx > Subject: [PATCH v2 1/4] dt-bindings: soc: imx8mp-hsio-blk-ctrl: add clock cells > > The HSIO blk-ctrl has a internal PLL, which can be used as a reference clock for > the PCIe PHY. Add clock-cells to the binding to allow the driver to expose this > PLL. > > Signed-off-by: Lucas Stach <l.stach@xxxxxxxxxxxxxx> Thanks a lot for this series. Verified on i.MX8MP EVK board when internal PLL clock mode is enabled. Reviewed-and-Tested-by: Richard Zhu <hongxing.zhu@xxxxxxx> Best Regards Richard Zhu > --- > v2: fix clock-cells value > --- > .../devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git > a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml > b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml > index c29181a9745b..1fe68b53b1d8 100644 > --- > a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml > +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl > +++ .yaml > @@ -39,6 +39,9 @@ properties: > - const: pcie > - const: pcie-phy > > + '#clock-cells': > + const: 0 > + > clocks: > minItems: 2 > maxItems: 2 > @@ -85,4 +88,5 @@ examples: > power-domain-names = "bus", "usb", "usb-phy1", > "usb-phy2", "pcie", "pcie-phy"; > #power-domain-cells = <1>; > + #clock-cells = <0>; > }; > -- > 2.30.2
