On 16/12/22 03:11, Nishanth Menon wrote: > On 18:22-20221215, Mark Brown wrote: >> On Thu, Dec 15, 2022 at 11:54:11AM -0600, Nishanth Menon wrote: >>> On 16:09-20221215, Mark Brown wrote: >> >>>> That proposal looks really non-idiomatic and quite unusual, if there's a >>>> fixed voltage supply to the LDO I'd expect to see it modeled as a fixed >>>> voltage regulator. I'm not sure what the use of bypass here is trying >>>> to accomplish TBH. >> >>> The problem is this - the default NVM in the PMIC is setup such that >>> VSET value =3.3v and bypass bit set (makes sense since the vin=3.3v). >> >> This implies no voltage drop over the LDO? Sounds a bit suspect. > > Not the choice I'd probably have made ;) > >> >>> Now the constraint is bypass bit cannot be changed without the LDO >>> being switched off. >> Per https://www.ti.com/lit/ds/symlink/tps65219.pdf (7.3.6 Linear Regulators). LDOs have two modes: 1. Load switch mode: in this case, output voltages of 1.5V up to 5.5V are supported. 2 Linear regulator LDO mode where output voltage is programmable in the range of 0.6V to 3.4V in 50mV-steps with possibility of bypass. (CAUTION on page 25): A mode change between LDO(/bypass) and LSW-mode must only be performed, when this regulator is disabled! A change between LDO and bypass-mode (supported by LDO1 and LDO2 only) is supported during operation. So, seems like bypass can be toggled even with LDO on? [...] Regards Vignesh
