On Sun, Dec 11, 2022 at 03:48:57AM +0100, Marek Vasut wrote: > The i.MX SoCs have various clock configurations routed into the PCIe IP, > the list of clock is below. Document all those configurations in the DT > binding document. > > All SoCs: pcie, pcie_bus > 6QDL, 7D: + pcie_phy > 6SX: + pcie_phy pcie_inbound_axi > 8MQ: + pcie_phy pcie_aux > 8MM, 8MP: + pcie_aux > > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > Acked-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx> > Signed-off-by: Marek Vasut <marex@xxxxxxx> > --- > Cc: Fabio Estevam <festevam@xxxxxxxxx> > Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@xxxxxxxxxx> > Cc: Lucas Stach <l.stach@xxxxxxxxxxxxxx> > Cc: Richard Zhu <hongxing.zhu@xxxxxxx> > Cc: Rob Herring <robh+dt@xxxxxxxxxx> > Cc: Shawn Guo <shawnguo@xxxxxxxxxx> > Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx > Cc: NXP Linux Team <linux-imx@xxxxxxx> > To: devicetree@xxxxxxxxxxxxxxx > --- > V2: - Add AB from Alex > V3: - Duplicate clock-names maxItems to mx6sx and mx8mq compatibles > - Flatten the if-else structure > - The validation no longer works and introduces errors like these: > arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb: pcie@33800000: clock-names:2: 'pcie_phy' was expected > V4: - Reinstate minItems: for clock-names in main section, turn the > last two clock-names items into enums to cover all IP variants. > - Add another allOf entry for mx6q/mx6qp/mx7d clock-names list. > - Adjust clock maxItems in the allOf section. > V5: - No change > V6: - Add RB from Rob This should have also gone to PCI maintainers and list so they could pick it up. However, I'll apply the series. Rob
