On Mon, Dec 12, 2022 at 11:35 AM Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx> wrote: > These delays are added when specified per GPIO line and GPIO is set > to high level, including any active low flag. > > Signed-off-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx> As stated in the binding patch this can be considered as a global ramp-up for the entire chip, certainly there are not different driver stages on the different outputs (in that case it would be a pin control driver BTW). This is created to swipe the details of random board electronics under the carpet and this doesn't work because we already have consumers such as regulators specifying ramp-up on the consumer side. Yours, Linus Walleij
