On Mon, 05 Dec 2022 17:23:46 +0000,
Sebastian Reichel <sebastian.reichel@xxxxxxxxxxxxx> wrote:
>
> From: Kever Yang <kever.yang@xxxxxxxxxxxxxx>
>
> This initial version supports (single core) CPU, dma, interrupts, timers,
> UART and SDHCI. In short - everything necessary to boot Linux on this
> system on chip.
>
> The DT is split into rk3588 and rk3588s, which is a reduced version
> (i.e. with less peripherals) of the former.
>
> Signed-off-by: Yifeng Zhao <yifeng.zhao@xxxxxxxxxxxxxx>
> Signed-off-by: Elaine Zhang <zhangqing@xxxxxxxxxxxxxx>
> Signed-off-by: Sugar Zhang <sugar.zhang@xxxxxxxxxxxxxx>
> Signed-off-by: Kever Yang <kever.yang@xxxxxxxxxxxxxx>
> [rebase, squash and reword commit message]
> Signed-off-by: Sebastian Reichel <sebastian.reichel@xxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/rockchip/rk3588.dtsi | 58 +
> arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1672 +++++++++++++++++++++
> 2 files changed, 1730 insertions(+)
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3588.dtsi
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s.dtsi
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> new file mode 100644
> index 000000000000..ecdd2294cd42
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
> @@ -0,0 +1,1672 @@
[...]
> + pmu-a55 {
> + compatible = "arm,cortex-a55-pmu";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + pmu-a76 {
> + compatible = "arm,cortex-a76-pmu";
> + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + };
Two PMUs with the same PPI and no partition? This is totally
wrong. Please see how RK3399 does it, with each PMU having a PPI
partition allocated.
See the PMU binding for the details.
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + spll: clock-0 {
> + compatible = "fixed-clock";
> + clock-frequency = <702000000>;
> + clock-output-names = "spll";
> + #clock-cells = <0>;
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
You have a set of ARMv8.2 cores, which do have an interrupt for the
EL2 virtual timer. Please add this interrupt and while you're at it,
add the interrupt-names properties that are associated with them.
See the binding for the details.
[...]
> + gic: interrupt-controller@fe600000 {
> + compatible = "arm,gic-v3";
> + reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
> + <0x0 0xfe680000 0 0x100000>; /* GICR */
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + mbi-alias = <0x0 0xfe610000>;
> + mbi-ranges = <424 56>;
> + msi-controller;
> + #interrupt-cells = <3>;
> +
> + ppi-partitions {
> + interrupt-partition-0 {
> + affinity = <
> + &cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3
> + &cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3
> + >;
> + };
> + };
What is the purpose of having an interrupt partition that covers *all*
the CPUs? This makes zero sense. You need to:
- Bump #interrupt-cells to 4, as per the GIC binding
- Create PPI partitions to segregate the two CPU types
- Make the PMU devices use the corresponding PPI partition as per the binding
- Fix all the interrupt specifiers to use 4 cells instead of 3
Again, RK3399 got it right, and for once I'm advocating some sort of
copy/paste...
M.
--
Without deviation from the norm, progress is not possible.
