On 07/12/2022 07.38, Janne Grunau wrote: > The t8103 CPU nodes are missing the cache hierarchy information. The > cache hierarchy on Arm can not be detected and needs to be described in > DT. The OS scheduler can make use of this information for scheduling > decisions. > > The cache size information is based on various articles about the > processors. There's also an L3 system level cache (SLC). It's not > described here because SLCs typically have some MMIO interface which > would need to be described. > > Based on Rob Herring's patch adding cache properties and nodes for > t600x. > > Link: https://lore.kernel.org/asahi/20221122220619.659174-1-robh@xxxxxxxxxx/ > > Signed-off-by: Janne Grunau <j@xxxxxxxxxx> Acked-by: Hector Martin <marcan@xxxxxxxxx> Thanks! Applied to asahi-soc/dt. - Hector
