On 11/28/22 06:08, Lad, Prabhakar wrote: > Hi Geert, > > On Sun, Nov 27, 2022 at 9:55 AM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: >> >> Hi Prabhakar, >> >> On Sat, Nov 26, 2022 at 10:10 PM Lad, Prabhakar >> <prabhakar.csengg@xxxxxxxxx> wrote: >>> On Fri, Nov 25, 2022 at 7:43 PM Samuel Holland <samuel@xxxxxxxxxxxx> wrote: >>>> On 11/24/22 11:22, Prabhakar wrote: >>>>> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> >>>>> >>>>> On the AX45MP core, cache coherency is a specification option so it may >>>>> not be supported. In this case DMA will fail. As a workaround, firstly we >>>>> allocate a global dma coherent pool from which DMA allocations are taken >>>>> and marked as non-cacheable + bufferable using the PMA region as specified >>>>> in the device tree. Synchronization callbacks are implemented to >>>>> synchronize when doing DMA transactions. >>>>> >>>>> The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA) >>>>> block that allows dynamic adjustment of memory attributes in the runtime. >>>>> It contains a configurable amount of PMA entries implemented as CSR >>>>> registers to control the attributes of memory locations in interest. >>>>> >>>>> Below are the memory attributes supported: >>>>> * Device, Non-bufferable >>>>> * Device, bufferable >>>>> * Memory, Non-cacheable, Non-bufferable >>>>> * Memory, Non-cacheable, Bufferable >>>>> * Memory, Write-back, No-allocate >>>>> * Memory, Write-back, Read-allocate >>>>> * Memory, Write-back, Write-allocate >>>>> * Memory, Write-back, Read and Write-allocate >>>>> >>>>> This patch adds support to configure the memory attributes of the memory >>>>> regions as passed from the l2 cache node and exposes the cache management >>>>> ops. >>>> >>>> Forgive my ignorance, but why do you need both a DMA pool and explicit >>>> cache maintenance? Wouldn't the purpose of marking a memory region as >>>> permanently non-cacheable be to avoid cache maintenance? And likewise, >>>> if you are doing cache maintenance anyway, why does it matter if/how the >>>> memory is cacheable? >>>> >>> "Memory, Non-cacheable, Bufferable" raises an AXI signal for >>> transactions hence needing SW implementation for cache maintenance. >>> >>>>> More info about PMA (section 10.3): >>>>> Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf >>>>> >>>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> >> >>>>> +static int ax45mp_configure_pma_regions(struct device_node *np) >>>>> +{ >>>>> + const char *propname = "andestech,pma-regions"; >>>>> + u32 start, size, flags; >>>>> + unsigned int entry_id; >>>>> + unsigned int i; >>>>> + int count; >>>>> + int ret; >>>>> + >>>>> + count = of_property_count_elems_of_size(np, propname, sizeof(u32) * 3); >>>>> + if (count < 0) >>>>> + return count; >>>>> + >>>>> + if (count > AX45MP_MAX_PMA_REGIONS) >>>>> + return -EINVAL; >>>>> + >>>>> + for (i = 0, entry_id = 0 ; entry_id < count ; i += 3, entry_id++) { >>>>> + of_property_read_u32_index(np, propname, i, &start); >>>>> + of_property_read_u32_index(np, propname, i + 1, &size); >>>>> + of_property_read_u32_index(np, propname, i + 2, &flags); >>>>> + ret = ax45mp_sbi_set_pma(start, size, flags, entry_id); >>>>> + if (!ret) >>>>> + pr_err("Failed to setup PMA region 0x%x - 0x%x flags: 0x%x", >>>>> + start, start + size, flags); >>>>> + } >>>>> + >>>>> + return 0; >>>>> +} >>>> >>>> If firmware support is required to set up these PMA regions, why is >>>> Linux doing this at all? The firmware has access to the devicetree as >>>> well. It can set this up before entering S-mode, and then you don't need >>>> to expose this capability via an SBI extension. In fact, firmware could >>>> generate the reserved-memory node based on these regions at runtime (or >>>> vice versa). >>>> >>> That's a good point. I'll do some research on this and get back. >>> >>> Btw are there any existing examples where the firmware adds DT nodes? >> >> /memory, reserved-memory, optee on ARM, RPC status on R-Car Gen3/4, ... >> > On the TF-A we pass the FDT blob to u-boot and this does the magic. > > On the RISC-V what would be the correct approach? > - We setup the PMA regions in OpenSBI > - We provide a vendor specific EXT to check if the PMA is setup > - In u-boot ft_board_setup() callback add the reserved-memory node > > Does the above approach sound good or is there a better approach I'm missing? My suggestion was to fix up the DT in OpenSBI itself. See lib/utils/fdt/fdt_fixup.c in the OpenSBI source tree. There is also a platform hook for this. Then OpenSBI passes the FDT to U-Boot, and U-Boot passes it on to Linux. No SBI extension is needed in that case. If you optionally want your U-Boot to support loading a replacement FDT from disk, then ft_board_setup() would need to copy the reserved-memory nodes from U-Boot's control FDT to the loaded FDT. But this logic is the same for all reserved-memory nodes, including the one OpenSBI adds already. U-Boot has some code for this copying which you could reuse. Regards, Samuel
