On Mon, Nov 28, 2022 at 09:41:03AM -0800, Palmer Dabbelt wrote: > On Thu, 24 Nov 2022 05:42:20 PST (-0800), heiko@xxxxxxxxx wrote: > > Am Donnerstag, 24. November 2022, 14:04:41 CET schrieb Conor Dooley: > > > I used the wikipedia table for ordering extensions when updating the > > > pattern here in foo. > > > > ^ foo? :-) > > > > > Unfortunately that table did not match canonical order, as defined by > > > the RISC-V ISA Manual, which defines extension ordering in (what is > > > currently) Table 41, "Standard ISA extension names". Fix things up by > > > re-sorting v (vector) and adding p (packed-simd) & j (dynamic > > > languages). The e (reduced integer) and g (general) extensions are still > > > intentionally left out. > > > > > > Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5 > > > Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators") > > > Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > > > > So I have compared the new pattern to the isa manual, > > and it looks like the order checks out, so > > Which ISA manual? For me, isa manual is the above github repo. > There have been many mutually incompatible ISA string > encoding rules, at least one of them was a change to the extension ordering. > It's not entirely clear what the right answer is here, as we can't really > parse ISA strings without also knowing the version of the ISA manual we're > meant to parse them against. Maybe we just accept everything? I don't think accepting everything is the right thing to do. A minimal amount of validation is still needed here, but I think we can deprecate the DT property entirely & make it optional if a new-and-improved way of encoding the in DT is used. > IMO it's time to just stop using the ISA string. It's not a stable > interface, trying to treat it as such just leads to headaches. We should > just come up with some DT-specific way of encoding whatever HW features are > in question. Sure it'll be a bit of work to write that all down in the DT > bindings, but it's going to be way less work than trying to keep around all > this ISA string parsing code. I'm a glutton for punishment, I'll try and come up with some sort of other way to encode this information in DT that requires less parsing and validation. As I said on IRC, something that more resembles: if (of_property_wahtever("riscv,isa-foo")) { do_enable_foo() } > I know I've said the opposite before, but there's just been way too many > breakages here to assume they're going to stop. :upside_down_face: Either way, I think these two patches are worth taking in the mean time. > > Reviewed-by: Heiko Stuebner <heiko@xxxxxxxxx> > > > > > --- > > > Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > > > index e80c967a4fa4..b7462ea2dbe4 100644 > > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > > > @@ -80,7 +80,7 @@ properties: > > > insensitive, letters in the riscv,isa string must be all > > > lowercase to simplify parsing. > > > $ref: "/schemas/types.yaml#/definitions/string" > > > - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ > > > + pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ > > > > > > # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here > > > timebase-frequency: false > > >
