On Fri, Nov 25, 2022 at 04:51:05PM +0530, Anup Patel wrote:
> We should set CLOCK_EVT_FEAT_C3STOP for a clock_event_device only
> when riscv,timer-cant-wake-up DT property is present in the RISC-V
> timer DT node.
>
> This way CLOCK_EVT_FEAT_C3STOP feature is set for clock_event_device
> based on RISC-V platform capabilities rather than having it set for
> all RISC-V platforms.
I need to go do some testing on what setting the C3STOP flag does on
platforms other than PolarFire SoC. I'm not sure that we should be
enabling this flag *at all* until we know that it does not break on
other platforms too.
Hopefully I'll get to it tonight or tomorrow..
> Signed-off-by: Anup Patel <apatel@xxxxxxxxxxxxxxxx>
> ---
> drivers/clocksource/timer-riscv.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> index a0d66fabf073..0c8bdd168a45 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -28,6 +28,7 @@
> #include <asm/timex.h>
>
> static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
> +static bool riscv_timer_cant_wake_cpu;
>
> static int riscv_clock_next_event(unsigned long delta,
> struct clock_event_device *ce)
> @@ -85,6 +86,8 @@ static int riscv_timer_starting_cpu(unsigned int cpu)
>
> ce->cpumask = cpumask_of(cpu);
> ce->irq = riscv_clock_event_irq;
> + if (riscv_timer_cant_wake_cpu)
> + ce->features |= CLOCK_EVT_FEAT_C3STOP;
> clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
>
> enable_percpu_irq(riscv_clock_event_irq,
> @@ -139,6 +142,13 @@ static int __init riscv_timer_init_dt(struct device_node *n)
> if (cpuid != smp_processor_id())
> return 0;
>
> + child = of_find_compatible_node(NULL, NULL, "riscv,timer");
> + if (child) {
> + riscv_timer_cant_wake_cpu = of_property_read_bool(child,
> + "riscv,timer-cant-wake-cpu");
> + of_node_put(child);
> + }
> +
> domain = NULL;
> child = of_get_compatible_child(n, "riscv,cpu-intc");
> if (!child) {
> --
> 2.34.1
>
