On Thu, Nov 24, 2022 at 9:06 PM Conor Dooley <conor.dooley@xxxxxxxxxxxxx> wrote: > > The RISC-V ISA Manual allows for the first Additional Standard > Extension having no leading underscore. Only if there are multiple > Additional Standard Extensions is it needed to have an underscore. > > The dt-binding does not validate that a multi-letter extension is > canonically ordered, as that'd need an even worse regex than is here, > but it should not fail validation for valid ISA strings. > > Allow the first Z multi-letter extension to appear immediately prior > after the single-letter extensions. > > Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5 > Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators") > Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index 90a7cabf58fe..e80c967a4fa4 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -80,7 +80,7 @@ properties: > insensitive, letters in the riscv,isa string must be all > lowercase to simplify parsing. > $ref: "/schemas/types.yaml#/definitions/string" > - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$ > + pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ Acked-by: Guo Ren <guoren@xxxxxxxxxx> > > # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here > timebase-frequency: false > -- > 2.38.1 > -- Best Regards Guo Ren
