Re: [linux-next-v2 4/5] arm64: dts: rockchip: Add support of interrupt to ethernet node on Rock 3A SBC

[Michael Riesch <michael.riesch@xxxxxxxxxxxxxx>]

Hi Anand,

On 11/16/22 21:01, Anand Moon wrote:
> As per the shematic gmac1 support gpio interrupt controller 

Typo "shematic" -> "schematic"

> GMAC1_INT/PMEB_GPIO3_A7 add the support for this.

Maybe split the commit message into two proper sentences.
> 
> Signed-off-by: Anand Moon <linux.amoon@xxxxxxxxx>
> ---
> v2: new patch added
> ---
>  arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
> index 5378254c57ca..9f84a23a8789 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
> @@ -588,10 +588,14 @@ rgmii_phy1: ethernet-phy@0 {
>  		compatible = "ethernet-phy-ieee802.3-c22";
>  		reg = <0x0>;
>  		pinctrl-names = "default";
> -		pinctrl-0 = <&eth_phy_rst>;
> +		pinctrl-0 = <&eth_phy_rst>, <&eth_phy_int>;
>  		reset-assert-us = <20000>;
>  		reset-deassert-us = <100000>;
>  		reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
> +		interrupt-parent = <&gpio3>;
> +		/* GMAC1_INT/PMEB_GPIO3_A7 */

This comment is pretty superfluous.

> +		interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
> +		#interrupt-cells = <1>;

I am not an expert here, but I believe #interrupt-cells = <1>; means
that the phy provides an array of interrupts. Are you sure this is
correct? I find it strange that the phy driver consumes one interrupt
and provides N interrupts?!

>  	};
>  };
>  
> @@ -630,6 +634,10 @@ vcc_mipi_en: vcc_mipi_en {
>  	};
>  
>  	ethernet {
> +		eth_phy_int: eth-phy-int {
> +			rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>;

Interrupt is active low and you pull down the line here? There is a pull
up resistor on sheet 11 of the schematic, so this does not seem right at
all.

Best regards,
Michael

> +		};
> +
>  		eth_phy_rst: eth_phy_rst {
>  			rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
>  		};