Hi Peter,
On Fri, 18 Nov 2022 at 00:40, Peter Geis <pgwipeout@xxxxxxxxx> wrote:
>
> On Thu, Nov 17, 2022 at 9:56 AM Anand Moon <linux.amoon@xxxxxxxxx> wrote:
> >
> > Hi Robin
> >
> > On Thu, 17 Nov 2022 at 16:24, Robin Murphy <robin.murphy@xxxxxxx> wrote:
> > >
> > > On 2022-11-17 05:57, Anand Moon wrote:
> > > > Hi Peter,
> > > >
> > > > On Thu, 17 Nov 2022 at 02:16, Peter Geis <pgwipeout@xxxxxxxxx> wrote:
> > > >>
> > > >> On Wed, Nov 16, 2022 at 3:02 PM Anand Moon <linux.amoon@xxxxxxxxx> wrote:
> > > >>>
> > > >>> Add MDIO description with ethernet-phy-id compatible string
> > > >>> which enable calling reset of the phy. The PHY will then be probed,
> > > >>> independent of if it can be found on the bus or not,
> > > >>> and that probing will enable the GPIO.
> > > >>>
> > > >>> ethernet-phy-id is read from ethenet register dump reg2 and reg3.
> > > >>>
> > > >>> Fix following warning.
> > > >>> [ 12.323417] rk_gmac-dwmac fe010000.ethernet eth0: Register MEM_TYPE_PAGE_POOL RxQ-0
> > > >>> [ 12.324078] rk_gmac-dwmac fe010000.ethernet eth0: no phy at addr -1
> > > >>> [ 12.324099] rk_gmac-dwmac fe010000.ethernet eth0: __stmmac_open: Cannot attach to PHY (error: -19)
> > > >>>
> > > >>> Signed-off-by: Anand Moon <linux.amoon@xxxxxxxxx>
> > > >>> ---
> > > >>> V2: new to the patch series.
> > > >>>
> > > >>> alarm@rock-3a:~$ sudo ethtool -d eth0
> > > >>> [sudo] password for alarm:
> > > >>> ST GMAC Registers
> > > >>> GMAC Registers
> > > >>> Reg0 0x08072203
> > > >>> Reg1 0x00000000
> > > >>> Reg2 0x00000404
> > > >>> Reg3 0x00000000
> > > >>> Reg4 0x00000002
> > > >>> ---
> > > >>> arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 2 +-
> > > >>> 1 file changed, 1 insertion(+), 1 deletion(-)
> > > >>>
> > > >>> diff --git a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
> > > >>> index 9f84a23a8789..fe36156a5017 100644
> > > >>> --- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
> > > >>> +++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
> > > >>> @@ -585,7 +585,7 @@ &i2s2_2ch {
> > > >>>
> > > >>> &mdio1 {
> > > >>> rgmii_phy1: ethernet-phy@0 {
> > > >>> - compatible = "ethernet-phy-ieee802.3-c22";
> > > >>> + compatible = "ethernet-phy-id0000.0404", "ethernet-phy-ieee802.3-c22";
> > > >>> reg = <0x0>;
> > > >>> pinctrl-names = "default";
> > > >>> pinctrl-0 = <ð_phy_rst>, <ð_phy_int>;
> > > >>
> > > >> Have you tried instead moving the reset to the mdio bus? I've had
> > > >> success with this, though you'll need to change the reset assert and
> > > >> deassert timing handles, they are different for the bus.
> > > >>
> > > > No can you share some examples?
> > > > If you got a better way to solve this issue please let me know.
> > > > I will give this a try.
> > >
> > > Note that the Rock 3A schematic says the phy is configured for address
> > > 1, not 0. From what I remember of adding the MDIO node for NanoiPi4,
> > > that didn't work if I got the address wrong, despite the fact that the
> > > auto-detection when the MDIO node is omitted claimed to find the same
> > > phy on both addresses 0 and 1.
> > >
>
> From the net-dev folk, mdio address 0 is a broadcast address. All
> functional phys we have on the mdio bus should respond to it. The
> problem I've run into is with the reset on the phy node the reset
> triggers too late for the dwmac to detect the phy correctly. However
> moving it to the mdio bus node makes the reset happen at roughly the
> same time as the depreciated dwmac reset and the phy detects without
> any weird hacks.
>
This is not a hack, we are already using mdio bus node.
&gma1 {
phy-handle=ethernet-phy
}
mdio1 {
ethernet-phy {
}
}
Actually, *ethernet-phy-id* is one of the binding properties (see below).
we can find many examples in the device tree that used this property in
the linux kernel and u-boot.
[0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/net/ethernet-phy.yaml?h=v6.1-rc6#n31
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/net/ethernet-phy.yaml?h=v6.1-rc6#n211
Please check this phy reset section below.
[2] https://wiki.st.com/stm32mpu/wiki/Ethernet_device_tree_configuration#RMII_with_25MHz_on_ETH_CLK_-28no_PHY_Crystal-29-2C_REF_CLK_from_PHY_-28Reference_clock_-28standard_RMII_clock_name-29_is_provided_by_a_PHY-29
If you have some other input please share I have tried but failed.
Thanks
-Anand
