Add Versal clocking wizard IP driver support The Versal clocking wizard is clock circuits customized to cater to clocking requirements. It provides configurable number of outputs. Datasheet: https://docs.xilinx.com/r/en-US/pg321-clocking-wizard Changes in v3: rename the clocks to clk_in1 and s_axi_clk dt rename the clocks to clk_in1 and s_axi_clk in driver Changes in v2: rename the clocks clk_in1 to in1 and s_axi_clk to s_axi in dt rename the clocks clk_in1 to in1 and s_axi_clk to s_axi in driver update the warn Update the compatible to reflect versal Shubhrajyoti Datta (2): dt-bindings: clk: Add binding for versal clocking wizard clocking-wizard: Add versal clocking wizard support .../clock/xlnx,versal-clk-wizard.yaml | 65 ++ drivers/clk/xilinx/Kconfig | 13 + drivers/clk/xilinx/Makefile | 1 + drivers/clk/xilinx/clk-xlnx-clock-wizard-v.c | 739 ++++++++++++++++++ 4 files changed, 818 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/xlnx,versal-clk-wizard.yaml create mode 100644 drivers/clk/xilinx/clk-xlnx-clock-wizard-v.c -- 2.17.1
