On some SoCs the System CIRQ register layout is slightly different, as there are more registers per function and in some cases other differences later in the layout: this is seen on at least MT8192, but it's also valid for some other "contemporary" SoCs both for Chromebooks and for smartphones. Add the new "v2" register layout and use it if the compatible "mediatek,mt8192-cirq" is found; to retain compatibility with older devicetrees and/or with SoCs that don't need any register layout variation, if no "special" compatible is found, we use the "v1" register layout by default. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx> --- drivers/irqchip/irq-mtk-cirq.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-mtk-cirq.c b/drivers/irqchip/irq-mtk-cirq.c index affbc0f48550..8d6b3d9c40cf 100644 --- a/drivers/irqchip/irq-mtk-cirq.c +++ b/drivers/irqchip/irq-mtk-cirq.c @@ -40,6 +40,18 @@ static const u32 mtk_cirq_regs_v1[] = { [CIRQ_CONTROL] = 0x300, }; +static const u32 mtk_cirq_regs_v2[] = { + [CIRQ_STA] = 0x0, + [CIRQ_ACK] = 0x80, + [CIRQ_MASK_SET] = 0x180, + [CIRQ_MASK_CLR] = 0x200, + [CIRQ_SENS_SET] = 0x300, + [CIRQ_SENS_CLR] = 0x380, + [CIRQ_POL_SET] = 0x480, + [CIRQ_POL_CLR] = 0x500, + [CIRQ_CONTROL] = 0x600, +}; + #define CIRQ_EN 0x1 #define CIRQ_EDGE 0x2 #define CIRQ_FLUSH 0x4 @@ -262,12 +274,15 @@ static inline void mtk_cirq_syscore_init(void) {} #endif static const struct of_device_id mtk_cirq_of_match[] = { - { .compatible = "mediatek, + { .compatible = "mediatek,mt8192-cirq", .data = &mtk_cirq_regs_v2 }, + { /* sentinel */ } +}; static int __init mtk_cirq_of_init(struct device_node *node, struct device_node *parent) { struct irq_domain *domain, *domain_parent; + const struct of_device_id *match; unsigned int irq_num; int ret; @@ -298,7 +313,11 @@ static int __init mtk_cirq_of_init(struct device_node *node, if (ret) goto out_unmap; - cirq_data->regs = mtk_cirq_regs_v1; + match = of_match_node(mtk_cirq_of_match, node); + if (match) + cirq_data->regs = match->data; + else + cirq_data->regs = mtk_cirq_regs_v1; irq_num = cirq_data->ext_irq_end - cirq_data->ext_irq_start + 1; domain = irq_domain_add_hierarchy(domain_parent, 0, -- 2.38.1