From: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>
Add an example to the rockchip-isp1 DT binding that showcases usage of
the parallel input of the ISP, connected to the CSI-2 receiver internal
to the i.MX8MP.
Signed-off-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>
---
.../bindings/media/rockchip-isp1.yaml | 72 +++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/rockchip-isp1.yaml b/Documentation/devicetree/bindings/media/rockchip-isp1.yaml
index 95cf945f7ac5..88d9bc378f79 100644
--- a/Documentation/devicetree/bindings/media/rockchip-isp1.yaml
+++ b/Documentation/devicetree/bindings/media/rockchip-isp1.yaml
@@ -285,3 +285,75 @@ examples:
};
};
};
+
+ - |
+ #include <dt-bindings/clock/imx8mp-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/media/video-interfaces.h>
+ #include <dt-bindings/power/imx8mp-power.h>
+
+ parent2: parent {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ isp@32e10000 {
+ compatible = "fsl,imx8mp-isp";
+ reg = <0x32e10000 0x10000>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+ clock-names = "isp", "hclk", "aclk";
+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_ISP>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+ assigned-clock-rates = <500000000>;
+ power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
+ fsl,blk-ctrl = <&media_blk_ctrl 0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ isp0_in: endpoint {
+ bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
+ remote-endpoint = <&mipi_csi_0_out>;
+ };
+ };
+ };
+ };
+
+ csi@32e40000 {
+ compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
+ reg = <0x32e40000 0x10000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <500000000>;
+ clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
+ clock-names = "pclk", "wrap", "phy", "axi";
+ assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
+ assigned-clock-rates = <500000000>;
+ power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ mipi_csi_0_out: endpoint {
+ remote-endpoint = <&isp0_in>;
+ };
+ };
+ };
+ };
+ };
+...
--
2.35.1
