Add configuration for dp83867 PHY LED mode via ti,led-modes property. Signed-off-by: Tim Harvey <tharvey@xxxxxxxxxxxxx> --- arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts | 6 ++++++ arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts | 6 ++++++ 3 files changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi index c305e325d007..bb9928153ff0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi @@ -111,6 +111,12 @@ ethphy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,led-modes = < + DP83867_LED_SEL_LINK + DP83867_LED_SEL_LINK_1000BT + DP83867_LED_SEL_LINK_ACT + DP83867_LED_SEL_LINK + >; tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index 11481e09c75b..d7de555cf5e1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -253,6 +253,12 @@ ethphy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,led-modes = < + DP83867_LED_SEL_LINK + DP83867_LED_SEL_LINK_1000BT + DP83867_LED_SEL_LINK_ACT + DP83867_LED_SEL_LINK + >; tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts index 97582db71ca8..8e61966c8dd0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts @@ -248,6 +248,12 @@ ethphy0: ethernet-phy@0 { reg = <0>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,led-modes = < + DP83867_LED_SEL_LINK + DP83867_LED_SEL_LINK_1000BT + DP83867_LED_SEL_LINK_ACT + DP83867_LED_SEL_LINK + >; tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; }; -- 2.25.1