Hi Geert and Guenter,
Thank you for your reviews!
As it turns out, the rzg2l_wdt driver has some reset related issues
(currently not addressed by the driver) for the RZ/V2M and RZ/Five
SoCs. More specifically to this patch, there is a better way to fix
the restart callback by addressing the way the reset is handled
for the watchdog IP.
I am dropping this patch, and I'll send out a series to address
the above concerns (which will tackle the issues with the restart
callback in a better way).
Thanks,
Fab
> From: Guenter Roeck <groeck7@xxxxxxxxx> On Behalf Of Guenter Roeck
> Sent: 15 November 2022 13:28
> Subject: Re: [PATCH 1/3] watchdog: rzg2l_wdt: Fix reboot for RZ/V2M
>
> On Thu, Nov 03, 2022 at 10:39:54PM +0000, Fabrizio Castro wrote:
> > The setting for the RZ/V2M watchdog cannot be changed once
> > the watchdog has been enabled, unless the IP gets reset.
> > The current implementation of the restart callback assumes
> > that the watchdog is not enabled, but that's not always the
> > case, and it leads to longer than necessary reboot times if
> > the watchdog is already running.
> >
> > Always reset the RZ/V2M watchdog first, so that we can always
> > restart quickly.
> >
> > Fixes: ec122fd94eeb ("watchdog: rzg2l_wdt: Add rzv2m support")
> > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>
>
> Reviewed-by: Guenter Roeck <linux@xxxxxxxxxxxx>
>
> > ---
> > drivers/watchdog/rzg2l_wdt.c | 11 ++++++++---
> > 1 file changed, 8 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/watchdog/rzg2l_wdt.c b/drivers/watchdog/rzg2l_wdt.c
> > index 974a4194a8fd..00438ceed17a 100644
> > --- a/drivers/watchdog/rzg2l_wdt.c
> > +++ b/drivers/watchdog/rzg2l_wdt.c
> > @@ -145,10 +145,10 @@ static int rzg2l_wdt_restart(struct
> watchdog_device *wdev,
> > {
> > struct rzg2l_wdt_priv *priv = watchdog_get_drvdata(wdev);
> >
> > - clk_prepare_enable(priv->pclk);
> > - clk_prepare_enable(priv->osc_clk);
> > -
> > if (priv->devtype == WDT_RZG2L) {
> > + clk_prepare_enable(priv->pclk);
> > + clk_prepare_enable(priv->osc_clk);
> > +
> > /* Generate Reset (WDTRSTB) Signal on parity error */
> > rzg2l_wdt_write(priv, 0, PECR);
> >
> > @@ -157,6 +157,11 @@ static int rzg2l_wdt_restart(struct watchdog_device
> *wdev,
> > } else {
> > /* RZ/V2M doesn't have parity error registers */
> >
> > + reset_control_reset(priv->rstc);
> > +
> > + clk_prepare_enable(priv->pclk);
> > + clk_prepare_enable(priv->osc_clk);
> > +
> > wdev->timeout = 0;
> >
> > /* Initialize time out */
> > --
> > 2.34.1
> >
