Hi Prabhakar,
On Mon, Nov 7, 2022 at 6:53 PM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Add required properties in pinctrl node to handle GPIO interrupts.
>
> Note as IRQC is not enabled in RZ/Five the phandle for interrupt-parent
> is added in RZ/G2UL specific dtsi so that RZ/Five pinctrl driver
> continues without waiting for IRQC to probe.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> @@ -531,6 +531,8 @@ pinctrl: pinctrl@11030000 {
> gpio-controller;
> #gpio-cells = <2>;
> gpio-ranges = <&pinctrl 0 0 152>;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
> power-domains = <&cpg>;
> resets = <&cpg R9A07G043_GPIO_RSTN>,
> diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
> index 7a8ed7ae253b..65e7b029361e 100644
> --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
> @@ -98,6 +98,10 @@ &irqc {
> resets = <&cpg R9A07G043_IA55_RESETN>;
> };
>
> +&pinctrl {
> + interrupt-parent = <&irqc>;
> +};
Do you plan to move it back to the common r9a07g043.dtsi later?
Perhaps it makes sense to move the full irqc node to r9a07g043[uf].dtsi?
There is not that much common left, even the compatible value differs.
We don't keep the few common properties of the cpu0 node in
r9a07g043.dtsi neither.
> +
> &soc {
> interrupt-parent = <&gic>;
>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
