[AMD Official Use Only - General]
From: Rob Herring <robh@xxxxxxxxxx>
Sent: Wednesday, November 16, 2022 2:30 PM
>> v8:
>> - Apply review request changes and picked the two unique examples
>> for the 4 chip-selects as one has the reset control support and
>> the other an interrupt. Missed the --in-reply-to in git
>> send-email for v7, included in this update.
>
>No, you haven't. By default in git, you don't have to do anything. See
>--thread and --no-chain-reply-to options. If you are messing with
>--in-reply-to, you are doing it wrong.
>
>Please resend the whole series properly threaded.
Will resend the series
>> diff --git a/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml b/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml
>> new file mode 100644
>> index 000000000000..622c93402a86
>> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml
>> @@ -0,0 +1,60 @@
...
>> +
>> +title: AMD Pensando Elba SoC Resource Controller
>> +
>> +description: |
>> + AMD Pensando Elba SoC Resource Controller functions are
>> + accessed with four chip-selects. Reset control is on CS0.
>
> One device with 4 chip-selects? Then I'd expect 'reg = <0 1 2 3>;'
>
> Hard to say more because I don't have the whole thread nor remember what
> exactly we discussed before. That was 100s of bindings ago...
I agree and the example for v7 had all 4 chip-selects shown. This is not a pick and
choose device on what functions to use for a usable system. Krzysztof requested
only showing two chip-selects in the example.
...
>> +examples:
>> + - |
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> + spi {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + num-cs = <4>;
>> +
>> + system-controller@0 {
>> + compatible = "amd,pensando-elbasr";
>> + reg = <0>;
>> + spi-max-frequency = <12000000>;
>> + #reset-cells = <1>;
>> + };
>> +
>> + system-controller@2 {
>> + compatible = "amd,pensando-elbasr";
>> + reg = <2>;
>> + spi-max-frequency = <12000000>;
>> + interrupt-parent = <&porta>;
>> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
>> + };
>> + };
Regards,
Brad
