On Wed, Nov 16, 2022 at 01:55:03PM +0000, daire.mcnamara@xxxxxxxxxxxxx wrote: > From: Daire McNamara <daire.mcnamara@xxxxxxxxxxxxx> > > On Microchip PolarFire SoC the PCIe rootport is behind a set of fabric > inter connect (fic) busses that encapsulate busses like ABP/AHP, AXI-S > and AXI-M. Depending on which fic(s) the rootport is wired through to > cpu space, the rootport driver needs to take account of the address > translation done by a parent (e.g. fabric) node before setting up its > own inbound address translation tables from attached devices. Hi Daire, minor nits: s/inter connect/interconnect/ s/fic/FIC/ ? Sounds like an initialism similar to ABP, AHP, etc? s/busses/buses/ Both ok, but "buses" much more common in drivers/pci/ s/cpu/CPU/ s/rootport/Root Port/ I try to follow PCIe spec usage. Below you use "root port" (with a space). At least add the space to make consistent here. Some apply to previous commit logs, too, IIRC. > + /* > + * check for one level up; will need to adjust > + * address translation tables for these Wrap to fill 78 columns or so. Most existing comments in the file are also capitalized per normal English conventions.
