On 16/11/2022 13:35, Abel Vesa wrote:
Add compatibles for both PCIe G4 and G3 found on SM8550. Also add the cnoc_pcie_sf_axi clock needed by the SM8550. Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> Konrad
drivers/pci/controller/dwc/pcie-qcom.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 6ac28ea8d67d..4a62b2500c1d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -181,7 +181,7 @@ struct qcom_pcie_resources_2_3_3 {/* 6 clocks typically, 7 for sm8250 */struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[12]; + struct clk_bulk_data clks[13]; int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; @@ -1206,6 +1206,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) res->clks[idx++].id = "noc_aggr_4"; res->clks[idx++].id = "noc_aggr_south_sf"; res->clks[idx++].id = "cnoc_qx"; + res->clks[idx++].id = "cnoc_pcie_sf_axi";num_opt_clks = idx - num_clks;res->num_clks = idx; @@ -1752,6 +1753,8 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-sm8550-pcie0", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-sm8550-pcie1", .data = &cfg_1_9_0 }, { } };
