Add dt bindings for the Renesas PhiClock clock generator. Signed-off-by: Alex Helms <alexander.helms.jy@xxxxxxxxxxx> --- .../bindings/clock/renesas,phiclock.yaml | 81 +++++++++++++++++++ MAINTAINERS | 5 ++ 2 files changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,phiclock.yaml diff --git a/Documentation/devicetree/bindings/clock/renesas,phiclock.yaml b/Documentation/devicetree/bindings/clock/renesas,phiclock.yaml new file mode 100644 index 000000000..2b36534d3 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,phiclock.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,phiclock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas PhiClock Clock Generator Device Tree Bindings + +maintainers: + - Alex Helms <alexander.helms.jy@xxxxxxxxxxx> + +description: | + The Renesas PhiClock is a programmable I2C clock generator that provides + 1 reference output and 2 clock outputs. + + The driver supports spread spectrum but only if all configurations use the + same spread spectrum parameters. If your configuration uses spread spectrum, + you must include renesas,ss-amount-percent, renesas,ss-modulation-hz, and + renesas,ss-direction in the device tree. + +properties: + '#clock-cells': + const: 1 + + clock-names: + items: + - const: xin-clkin + + clocks: + const: 1 + + compatible: + enum: + - renesas,9fgv1006 + + reg: + maxItems: 1 + + renesas,ss-amount-percent: + description: Spread spectrum absolute amount as hundredths of a percent, e.g. 150 is 1.50%. + minimum: 0 + maximum: 500 + + renesas,ss-modulation-hz: + description: Spread spectrum modulation rate in Hz + minimum: 30000 + maximum: 63000 + + renesas,ss-direction: + $ref: /schemas/types.yaml#/definitions/string + description: Spread spectrum direction + enum: [ down, center ] + +required: + - clock-names + - '#clock-cells' + - compatible + - reg + +additionalProperties: false + +examples: + - | + ref25: ref25m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + phiclock: clock-controller@68 { + compatible = "renesas,9fgv1006"; + reg = <0x68>; + #clock-cells = <1>; + clocks = <&ref25>; + clock-names = "xin-clkin"; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 256f03904..7eabe930b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17641,6 +17641,11 @@ S: Maintained F: Documentation/devicetree/bindings/clock/renesas,versaclock7.yaml F: drivers/clk/clk-versaclock7.c +RENESAS PHICLOCK CLOCK DRIVER +M: Alex Helms <alexander.helms.jy@xxxxxxxxxxx> +S: Maintained +F: Documentation/devicetree/bindings/clock/renesas,phiclock.yaml + RESET CONTROLLER FRAMEWORK M: Philipp Zabel <p.zabel@xxxxxxxxxxxxxx> S: Maintained -- 2.25.1
