> + u32 mdio_freq = MAX_MDIO_FREQ;
> /* clk_div can be calculated by deriving it from the equation:
> * fMDIO = fHOST / ((1 + clk_div) * 2)
A nit pick, but MAX_MDIO_FREQ is not actually the max. The max would
be clk_div = 0. You can run the MDIO bus faster than 2.5MHz, if you
know all the devices on the bus actually support faster speeds. I've
run it at 6Mhz with Marvell Ethernet switches and PHYs.
DEFAULT_MDIO_FREQ would be better.
> *
> @@ -209,13 +218,20 @@ static int axienet_mdio_enable(struct axienet_local *lp)
> * "clock-frequency" from the CPU
> */
>
> - lp->mii_clk_div = (host_clock / (MAX_MDIO_FREQ * 2)) - 1;
> + clk_div = (host_clock / (mdio_freq * 2)) - 1;
> /* If there is any remainder from the division of
> - * fHOST / (MAX_MDIO_FREQ * 2), then we need to add
> + * fHOST / (mdio_freq * 2), then we need to add
> * 1 to the clock divisor or we will surely be above 2.5 MHz
s/2.5 MHz/the requested frequency/
With these changes made:
Reviewed-by: Andrew Lunn <andrew@xxxxxxx>
Andrew
