The sun6i DPHY can generate several interrupts, mostly for reporting
error conditions, but also for detecting BTA and UPLS sequences.
Document this capability in order to accurately describe the hardware.
The DPHY has no interrupt number provided in the vendor documentation
because its interrupt line is shared with the DSI controller.
A trivial interrupt handler was used to verify that interrupts were in
fact generated by the DPHY and not the DSI controller.
Signed-off-by: Samuel Holland <samuel@xxxxxxxxxxxx>
---
Changes in v2:
- Add the interrupts property to the binding example
- Drop the inappropriate Fixes tags
.../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
index dfb6a8993535..4c45d7fcc853 100644
--- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
+++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
@@ -24,6 +24,9 @@ properties:
reg:
maxItems: 1
+ interrupts:
+ maxItems: 1
+
clocks:
items:
- description: Bus Clock
@@ -53,6 +56,7 @@ required:
- "#phy-cells"
- compatible
- reg
+ - interrupts
- clocks
- clock-names
- resets
@@ -61,9 +65,12 @@ additionalProperties: false
examples:
- |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
dphy0: d-phy@1ca1000 {
compatible = "allwinner,sun6i-a31-mipi-dphy";
reg = <0x01ca1000 0x1000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu 23>, <&ccu 97>;
clock-names = "bus", "mod";
resets = <&ccu 4>;
--
2.37.3
