On Mon, 07 Nov 2022 23:49:19 +0300, Serge Semin wrote:
> It's normal to have the DW PCIe RP/EP DT-nodes equipped with the explicit
> PHY phandle references. There can be up to 16 PHYs attach in accordance
> with the maximum number of supported PCIe lanes. Let's extend the common
> DW PCIe controller schema with the 'phys' and 'phy-names' properties
> definition. There two types PHY names are defined: preferred generic names
> '^pcie[0-9]+$' and non-preferred vendor-specific names
> '^pcie([0-9]+|-?phy[0-9]*)?$' so to match the names currently supported by
> the DW PCIe platform drivers ("pcie": meson; "pciephy": qcom, imx6;
> "pcie-phy": uniphier, rockchip, spear13xx; "pcie": intel-gw; "pcie-phy%d":
> keystone, dra7xx; "pcie": histb, etc).
>
> Signed-off-by: Serge Semin <Sergey.Semin@xxxxxxxxxxxxxxxxxxxx>
>
> ---
>
> Changelog v3:
> - This is a new patch unpinned from the next one:
> https://lore.kernel.org/linux-pci/20220503214638.1895-2-Sergey.Semin@xxxxxxxxxxxxxxxxxxxx/
> by the Rob' request. (@Rob)
>
> Changelog v5:
> - Add a note about having line-based PHY phandles order. (@Rob)
> - Prefer 'pcie[0-9]+' PHY-names over the rest of the cases. (@Rob)
>
> Changelog v6:
> - Add the Nvidia Tegra194-specific "p2u-[0-7]" phy-names too. (@DT-tbot)
> - Drop 'deprecated' keywords from the vendor-specific names. (@Rob)
> ---
> .../bindings/pci/snps,dw-pcie-common.yaml | 24 +++++++++++++++++++
> .../bindings/pci/snps,dw-pcie-ep.yaml | 3 +++
> .../devicetree/bindings/pci/snps,dw-pcie.yaml | 3 +++
> 3 files changed, 30 insertions(+)
>
Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
