[PATCH 1/2] dt-bindings: ufs: Add document for Unisoc UFS host controller

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From: Zhe Wang <zhe.wang1@xxxxxxxxxx>

Add Unisoc ums9620 ufs host controller devicetree document.

Signed-off-by: Zhe Wang <zhe.wang1@xxxxxxxxxx>
---
 .../devicetree/bindings/ufs/sprd,ufs.yaml     | 72 +++++++++++++++++++
 1 file changed, 72 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/ufs/sprd,ufs.yaml

diff --git a/Documentation/devicetree/bindings/ufs/sprd,ufs.yaml b/Documentation/devicetree/bindings/ufs/sprd,ufs.yaml
new file mode 100644
index 000000000000..88f2c670b0a4
--- /dev/null
+++ b/Documentation/devicetree/bindings/ufs/sprd,ufs.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ufs/sprd,ufs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Unisoc Universal Flash Storage (UFS) Controller
+
+maintainers:
+  - Zhe Wang <zhe.wang1@xxxxxxxxxx>
+
+allOf:
+  - $ref: ufs-common.yaml
+
+properties:
+  compatible:
+    enum:
+      - sprd,ums9620-ufs
+
+  clocks:
+    maxItems: 2
+
+  clock-names:
+    items:
+      - const: hclk
+      - const: hclk_source
+
+  resets:
+    maxItems: 2
+
+  reset-names:
+    items:
+      - const: ufs_soft_rst
+      - const: ufsdev_soft_rst
+
+  sprd,ufs-anly-reg-syscon:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: phandle of syscon used to control ufs analog reg.
+
+  sprd,aon-apb-syscon:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: phandle of syscon used to control always-on reg.
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - resets
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    ufs: ufs@22000000 {
+        compatible = "sprd,ums9620-ufs";
+        reg = <0x22000000 0x3000>;
+        interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+        vcc-supply = <&vddemmcore>;
+        vdd-mphy-supply = <&vddufs1v2>;
+        clocks-name = "ufs_eb", "ufs_cfg_eb",
+            "ufs_hclk", "ufs_hclk_source";
+        clocks = <&apahb_gate CLK_UFS_EB>, <&apahb_gate CLK_UFS_CFG_EB>,
+            <&onapb_clk CLK_UFS_AON>, <&g51_pll CLK_TGPLL_256M>;
+        freq-table-hz = <0 0>, <0 0>, <0 0>, <0 0>;
+        reset-names = "ufs_soft_rst", "ufsdev_soft_rst";
+        resets = <&apahb_gate RESET_AP_AHB_UFS_SOFT_RST>,
+            <&aonapb_gate RESET_AON_APB_UFSDEV_SOFT_RST>;
+        sprd,ufs-anly-reg-syscon = <&anly_phy_g12_regs>;
+        sprd,aon-apb-syscon = <&aon_apb_regs>;
+        status = "disable";
+    };
-- 
2.17.1




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