Hi Marek, Am Mittwoch, 9. November 2022, 01:24:47 CET schrieb Marek Vasut: > The i.MX SoCs have various clock configurations routed into the PCIe IP, > the list of clock is below. Document all those configurations in the DT > binding document. > > All SoCs: pcie, pcie_bus > 6QDL, 7D: + pcie_phy > 6SX: + pcie_phy pcie_inbound_axi > 8MQ: + pcie_phy pcie_aux > 8MM, 8MP: + pcie_aux > > Acked-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx> > Signed-off-by: Marek Vasut <marex@xxxxxxx> I just noticed this is a separate series. Please note that there is already another patch doing the same at [1] Regards, Alexander [1] https://patchwork.kernel.org/project/linux-arm-kernel/patch/ 20221107204934.32655-2-Sergey.Semin@xxxxxxxxxxxxxxxxxxxx/ > --- > Cc: Fabio Estevam <festevam@xxxxxxxxx> > Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@xxxxxxxxxx> > Cc: Lucas Stach <l.stach@xxxxxxxxxxxxxx> > Cc: Richard Zhu <hongxing.zhu@xxxxxxx> > Cc: Rob Herring <robh+dt@xxxxxxxxxx> > Cc: Shawn Guo <shawnguo@xxxxxxxxxx> > Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx > Cc: NXP Linux Team <linux-imx@xxxxxxx> > To: devicetree@xxxxxxxxxxxxxxx > --- > V2: - Add AB from Alex > V3: - Duplicate clock-names maxItems to mx6sx and mx8mq compatibles > - Flatten the if-else structure > - The validation no longer works and introduces errors like these: > arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb: > pcie@33800000: clock-names:2: 'pcie_phy' was expected V4: - Reinstate > minItems: for clock-names in main section, turn the last two clock-names > items into enums to cover all IP variants. - Add another allOf entry for > mx6q/mx6qp/mx7d clock-names list. - Adjust clock maxItems in the allOf > section. > V5: - No change > --- > .../bindings/pci/fsl,imx6q-pcie.yaml | 73 +++++++++++++++++-- > 1 file changed, 68 insertions(+), 5 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index > 376e739bcad40..2df73be0ffbea 100644 > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > @@ -14,9 +14,6 @@ description: |+ > This PCIe host controller is based on the Synopsys DesignWare PCIe IP > and thus inherits all the common properties defined in snps,dw-pcie.yaml. > > -allOf: > - - $ref: /schemas/pci/snps,dw-pcie.yaml# > - > properties: > compatible: > enum: > @@ -60,8 +57,8 @@ properties: > items: > - const: pcie > - const: pcie_bus > - - const: pcie_phy > - - const: pcie_inbound_axi for imx6sx-pcie, pcie_aux for imx8mq-pcie > + - enum: [ pcie_phy, pcie_aux ] > + - enum: [ pcie_aux, pcie_inbound_axi ] > > num-lanes: > const: 1 > @@ -177,6 +174,72 @@ required: > > unevaluatedProperties: false > > +allOf: > + - $ref: /schemas/pci/snps,dw-pcie.yaml# > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - fsl,imx6q-pcie > + - fsl,imx6qp-pcie > + - fsl,imx7d-pcie > + then: > + properties: > + clocks: > + maxItems: 3 > + clock-names: > + items: > + - const: pcie > + - const: pcie_bus > + - const: pcie_phy > + > + - if: > + properties: > + compatible: > + contains: > + const: fsl,imx6sx-pcie > + then: > + properties: > + clock-names: > + items: > + - const: pcie > + - const: pcie_bus > + - const: pcie_phy > + - const: pcie_inbound_axi > + > + - if: > + properties: > + compatible: > + contains: > + const: fsl,imx8mq-pcie > + then: > + properties: > + clock-names: > + items: > + - const: pcie > + - const: pcie_bus > + - const: pcie_phy > + - const: pcie_aux > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - fsl,imx8mm-pcie > + - fsl,imx8mp-pcie > + then: > + properties: > + clocks: > + maxItems: 3 > + clock-names: > + items: > + - const: pcie > + - const: pcie_bus > + - const: pcie_aux > + > examples: > - | > #include <dt-bindings/clock/imx6qdl-clock.h>
