Some SoCs have one clock divider for all MMC units, thus changing one affects others as well. This leads to random hangs and memory corruptions, observed on the JZ4755 based device with two MMC slots used at the same time. List of SoCs affected includes: JZ4725b, JZ4755, JZ4760 and JZ4760b. The MMC core has its own clock divisor and it goes to the first plan in that case. Siarhei Volkau (2): mmc: jz4740: Don't change parent clock rate for some SoCs MIPS: ingenic: rs90: set MMC_MUX clock arch/mips/boot/dts/ingenic/rs90.dts | 5 +++-- drivers/mmc/host/jz4740_mmc.c | 10 +++++++++- 2 files changed, 12 insertions(+), 3 deletions(-) -- 2.36.1
