On Mon, Nov 07, 2022 at 04:56:53PM +0100, Pierre Gondois wrote: > v2: > - Update/Add patches for missed cache properties requiring to be > updated for the following platforns: bcm, amazon, arm, exynos, > freescale, marvell, mediatek, nvidia, socinext, tesla, ti. > Missed cache properties were detected using Rob Herring's branch: > https://github.com/robherring/dt-schema/tree/cache-rework > - v1 of exynos, tesla were merged. > - Updated wrong reference in commit message. > - Added received Rb/Acked-by. > > Align arm64 DTS to the DeviceTree specification v0.3 regarding > cache properties. The patch-set mainly adds 'cache-level' or > 'cache' compatibility properties. > For one qcom DTS, level 1 cache nodes are removed as they should > be in the cpu nodes. > > On another node, it seems that the 'cache-unified' is under-used. > cache-unified: > If present, specifies the cache has a unified or- > ganization. If not present, specifies that the > cache has a Harvard architecture with separate > caches for instructions and data. > Only a few l2 cache nodes have this property, and in the absence > of [|d|i]-cache-size properties (or other), the cache is assumed to be > split. > > The l2 cache of the Rockchip RK3308 platform is thus assumed to be > split: > l2: l2-cache { > compatible = "cache"; > cache-level = <2>; > }; > when the platform datasheet advertises a unified cache. > > No modification/check was made to correct that due to the lack of > cache information for most platforms. I suppose in theory a split L2 is possible, but I think in practice that doesn't exist. The Arm ARM allows for such a thing, but this[1] says L2 caches are unified. IMO, we should just define level 2+ is unified in the schema and we can relax that if ever needed. I've updated the cache schema branch[2] with that requirement. Rob [1] https://developer.arm.com/documentation/den0024/a/Caches/Cache-terminology [2] https://github.com/robherring/dt-schema/tree/cache-rework
