On 04/11/2022 18:04, Marek Vasut wrote: > The i.MX SoCs have various clock configurations routed into the PCIe IP, > the list of clock is below. Document all those configurations in the DT > binding document. > > All SoCs: pcie, pcie_bus > 6QDL, 7D: + pcie_phy > 6SX: + pcie_phy pcie_inbound_axi > 8MQ: + pcie_phy pcie_aux > 8MM, 8MP: + pcie_aux > > Acked-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx> > Signed-off-by: Marek Vasut <marex@xxxxxxx> > --- > Cc: Fabio Estevam <festevam@xxxxxxxxx> > Cc: Krzysztof Kozlowski <krzysztof.kozlowski+dt@xxxxxxxxxx> > Cc: Lucas Stach <l.stach@xxxxxxxxxxxxxx> > Cc: Richard Zhu <hongxing.zhu@xxxxxxx> > Cc: Rob Herring <robh+dt@xxxxxxxxxx> > Cc: Shawn Guo <shawnguo@xxxxxxxxxx> > Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx > Cc: NXP Linux Team <linux-imx@xxxxxxx> > To: devicetree@xxxxxxxxxxxxxxx > --- > V2: - Add AB from Alex > V3: - Duplicate clock-names maxItems to mx6sx and mx8mq compatibles > - Flatten the if-else structure > - The validation no longer works and introduces errors like these: > arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-dahlia.dtb: pcie@33800000: clock-names:2: 'pcie_phy' was expected > --- > .../bindings/pci/fsl,imx6q-pcie.yaml | 55 +++++++++++++++++-- > 1 file changed, 50 insertions(+), 5 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > index 376e739bcad40..44c65d3ec07b9 100644 > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml > @@ -14,9 +14,6 @@ description: |+ > This PCIe host controller is based on the Synopsys DesignWare PCIe IP > and thus inherits all the common properties defined in snps,dw-pcie.yaml. > > -allOf: > - - $ref: /schemas/pci/snps,dw-pcie.yaml# > - > properties: > compatible: > enum: > @@ -56,12 +53,10 @@ properties: > imx8mq-pcie. > > clock-names: > - minItems: 3 Why removing this and keeping it in clocks? They must be matching each other. > items: > - const: pcie > - const: pcie_bus > - const: pcie_phy > - - const: pcie_inbound_axi for imx6sx-pcie, pcie_aux for imx8mq-pcie It's now a bit confusing - you have different items and constraints in top-level clock-names than in if-else for specific variants. The usual convention for this is: 1. in top-level properties add clocks and clock-names with minItems and maxItems matching the widest possibility 2. In allOf:if:then you narrow them - with "items" or maxItems. Your setup probably works but it is confusing. Plus I am not sure if the names mentioned in top level clock-names are applicable now to anything... Best regards, Krzysztof
