Dne torek, 01. november 2022 ob 15:16:54 CET je Andre Przywara napisal(a):
> For some reason the mod clock for the Allwinner F1C100s CIR (infrared
> receiver) peripheral was not modeled in the CCU driver.
>
> Add the clock description to the list, and wire it up in the clock list.
> By assigning a new clock ID at the end, it extends the number of clocks.
>
> This allows to use the CIR peripheral on any F1C100s series board.
>
> Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx>
> ---
> drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c | 11 ++++++++++-
> drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h | 2 +-
> include/dt-bindings/clock/suniv-ccu-f1c100s.h | 2 ++
> 3 files changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
> b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c index
> ed097c4f780ff..af4811e720b39 100644
> --- a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
> +++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
> @@ -239,7 +239,14 @@ static SUNXI_CCU_MUX_WITH_GATE(i2s_clk, "i2s",
> i2s_spdif_parents, static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif",
> i2s_spdif_parents, 0x0b4, 16, 2, BIT(31), 0);
>
> -/* The BSP header file has a CIR_CFG, but no mod clock uses this definition
> */ +static const char * const ir_parents[] = { "osc32k", "osc24M" };
> +static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
> + ir_parents, 0x0b8,
> + 0, 4, /* M */
> + 16, 2, /* P */
> + 24, 1, /* mux */
Let's follow user manual here and make mux 2 bits wide. That way we'll
guarantee that bit 1 is always written 0.
Best regards,
Jernej
> + BIT(31), /* gate */
> + 0);
>
> static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
> 0x0cc, BIT(1), 0);
> @@ -355,6 +362,7 @@ static struct ccu_common *suniv_ccu_clks[] = {
> &mmc1_output_clk.common,
> &i2s_clk.common,
> &spdif_clk.common,
> + &ir_clk.common,
> &usb_phy0_clk.common,
> &dram_ve_clk.common,
> &dram_csi_clk.common,
> @@ -446,6 +454,7 @@ static struct clk_hw_onecell_data suniv_hw_clks = {
> [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
> [CLK_I2S] = &i2s_clk.common.hw,
> [CLK_SPDIF] = &spdif_clk.common.hw,
> + [CLK_IR] = &ir_clk.common.hw,
> [CLK_USB_PHY0] =
&usb_phy0_clk.common.hw,
> [CLK_DRAM_VE] =
&dram_ve_clk.common.hw,
> [CLK_DRAM_CSI] =
&dram_csi_clk.common.hw,
> diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
> b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h index
> b22484f1bb9a5..d56a4316289d8 100644
> --- a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
> +++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.h
> @@ -29,6 +29,6 @@
>
> /* All bus gates, DRAM gates and mod clocks are exported */
>
> -#define CLK_NUMBER (CLK_AVS + 1)
> +#define CLK_NUMBER (CLK_IR + 1)
>
> #endif /* _CCU_SUNIV_F1C100S_H_ */
> diff --git a/include/dt-bindings/clock/suniv-ccu-f1c100s.h
> b/include/dt-bindings/clock/suniv-ccu-f1c100s.h index
> f5ac155c9c70a..d7570765f424d 100644
> --- a/include/dt-bindings/clock/suniv-ccu-f1c100s.h
> +++ b/include/dt-bindings/clock/suniv-ccu-f1c100s.h
> @@ -67,4 +67,6 @@
> #define CLK_CODEC 65
> #define CLK_AVS 66
>
> +#define CLK_IR 67
> +
> #endif
