On Sat, 25 Oct 2014, Stephen Warren wrote:
> On 10/24/2014 09:53 AM, Lee Jones wrote:
> > On Fri, 24 Oct 2014, Lubomir Rintel wrote:
> >
> >> Follows the generic Mailbox Controller bindings as documented in
> >> Documentation/devicetree/bindings/mailbox/mailbox.txt.
> >>
> >> Signed-off-by: Lubomir Rintel <lkundrak@xxxxx>
> >> Cc: Stephen Warren <swarren@xxxxxxxxxxxxx>
> >> Cc: Lee Jones <lee.jones@xxxxxxxxxx>
> >> Cc: devicetree@xxxxxxxxxxxxxxx
> >> Cc: linux-rpi-kernel@xxxxxxxxxxxxxxxxxxx
> >> Cc: linux-arm-kernel@xxxxxxxxxxxxxxxxxxx
> >> ---
> >> arch/arm/boot/dts/bcm2835.dtsi | 7 +++++++
> >> 1 file changed, 7 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi
> >> index 3342cb1..bd046a9 100644
> >> --- a/arch/arm/boot/dts/bcm2835.dtsi
> >> +++ b/arch/arm/boot/dts/bcm2835.dtsi
> >> @@ -50,6 +50,13 @@
> >> #interrupt-cells = <2>;
> >> };
> >>
> >> + mailbox: mailbox@0x7e00b880 {
> >
> > Remove the 0x.
> >
> >> + compatible = "brcm,bcm2835-mbox";
> >> + reg = <0x7e00b880 0x40>;
> >> + interrupts = <0 1>;
> >
> > 2 interrupts one cell right? No flags?
>
> The DT binding says 1 IRQ in the list, and the interrupt controller in
> bcm2835.dtsi has 2 cells per IRQ.
>
> Whether that's all the IRQs the HW has for this HW module, I don't know.
Okay, so guessing <BANK INT> then. Very well, thanks for answering.
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