On 22-10-28 13:32:24, Shengjiu Wang wrote:
> From: Abel Vesa <abel.vesa@xxxxxxx>
>
> According to the RM, the CCGR101 is shared for the following root clocks:
> - AUDIO_AHB_CLK_ROOT
> - AUDIO_AXI_CLK_ROOT
> - SAI1_CLK_ROOT
> - SAI2_CLK_ROOT
> - SAI3_CLK_ROOT
> - SAI5_CLK_ROOT
> - SAI6_CLK_ROOT
> - SAI7_CLK_ROOT
> - PDM_CLK_ROOT
>
> And still keep MX8MP_CLK_AUDIO_ROOT clock, even it is duplicate with
> AUDIO_AHB_CLK_ROOT, that is to avoid break any users.
>
> Signed-off-by: Abel Vesa <abel.vesa@xxxxxxx>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@xxxxxxx>
> Reviewed-by: Peng Fan <peng.fan@xxxxxxx>
> ---
> drivers/clk/imx/clk-imx8mp.c | 17 ++++++++++++++++-
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index 652ae58c2735..d9ad09877990 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -17,6 +17,7 @@
>
> static u32 share_count_nand;
> static u32 share_count_media;
> +static u32 share_count_audio;
>
> static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
> static const char * const audio_pll1_bypass_sels[] = {"audio_pll1", "audio_pll1_ref_sel", };
> @@ -699,7 +700,21 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
> hws[IMX8MP_CLK_HDMI_ROOT] = imx_clk_hw_gate4("hdmi_root_clk", "hdmi_axi", ccm_base + 0x45f0, 0);
> hws[IMX8MP_CLK_TSENSOR_ROOT] = imx_clk_hw_gate4("tsensor_root_clk", "ipg_root", ccm_base + 0x4620, 0);
> hws[IMX8MP_CLK_VPU_ROOT] = imx_clk_hw_gate4("vpu_root_clk", "vpu_bus", ccm_base + 0x4630, 0);
> - hws[IMX8MP_CLK_AUDIO_ROOT] = imx_clk_hw_gate4("audio_root_clk", "audio_ahb", ccm_base + 0x4650, 0);
> +
> + /*
> + * IMX8MP_CLK_AUDIO_ROOT is same as IMX8MP_CLK_AUDIO_AHB_ROOT.
> + * In order to avoid break any users, still keep it.
> + */
> + hws[IMX8MP_CLK_AUDIO_ROOT] = imx_clk_hw_gate2_shared2("audio_root_clk", "audio_ahb", ccm_base + 0x4650, 0, &share_count_audio);
> + hws[IMX8MP_CLK_AUDIO_AHB_ROOT] = imx_clk_hw_gate2_shared2("audio_ahb_root", "audio_ahb", ccm_base + 0x4650, 0, &share_count_audio);
Please correct me if I'm wrong, but maybe it would make more sense to
register just one clock here and then do:
#define IMX8MP_CLK_AUDIO_AHB_ROOT IMX8MP_CLK_AUDIO_ROOT
in the bindings header file?
AFAIK, all consumers use these clocks by their binding ID.
> + hws[IMX8MP_CLK_AUDIO_AXI_ROOT] = imx_clk_hw_gate2_shared2("audio_axi_root", "audio_axi", ccm_base + 0x4650, 0, &share_count_audio);
> + hws[IMX8MP_CLK_SAI1_ROOT] = imx_clk_hw_gate2_shared2("sai1_root", "sai1", ccm_base + 0x4650, 0, &share_count_audio);
> + hws[IMX8MP_CLK_SAI2_ROOT] = imx_clk_hw_gate2_shared2("sai2_root", "sai2", ccm_base + 0x4650, 0, &share_count_audio);
> + hws[IMX8MP_CLK_SAI3_ROOT] = imx_clk_hw_gate2_shared2("sai3_root", "sai3", ccm_base + 0x4650, 0, &share_count_audio);
> + hws[IMX8MP_CLK_SAI5_ROOT] = imx_clk_hw_gate2_shared2("sai5_root", "sai5", ccm_base + 0x4650, 0, &share_count_audio);
> + hws[IMX8MP_CLK_SAI6_ROOT] = imx_clk_hw_gate2_shared2("sai6_root", "sai6", ccm_base + 0x4650, 0, &share_count_audio);
> + hws[IMX8MP_CLK_SAI7_ROOT] = imx_clk_hw_gate2_shared2("sai7_root", "sai7", ccm_base + 0x4650, 0, &share_count_audio);
> + hws[IMX8MP_CLK_PDM_ROOT] = imx_clk_hw_gate2_shared2("pdm_root", "pdm", ccm_base + 0x4650, 0, &share_count_audio);
>
> hws[IMX8MP_CLK_ARM] = imx_clk_hw_cpu("arm", "arm_a53_core",
> hws[IMX8MP_CLK_A53_CORE]->clk,
> --
> 2.34.1
>
