[PATCH 2/3] dt-bindings: pwm: rzg2l-gpt: Document renesas,poegs property

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RZ/G2L GPT IP supports output pin disable function by dead time
error and detecting short-circuits between output pins.

Add documentation for the optional property renesas,poegs to
link a pair of GPT IOs with POEG.

Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
---
 .../bindings/pwm/renesas,rzg2l-gpt.yaml       | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
index 620d5ae4ae30..32f9deae89e5 100644
--- a/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
+++ b/Documentation/devicetree/bindings/pwm/renesas,rzg2l-gpt.yaml
@@ -245,6 +245,24 @@ properties:
   resets:
     maxItems: 1
 
+  renesas,poegs:
+    $ref: "/schemas/types.yaml#/definitions/phandle-array"
+    items:
+      items:
+        - description: phandle to POEG instance that serves the output disable
+        - description: An index identifying pair of GPT channels.
+                       <0> - GPT channels 0 and 1
+                       <1> - GPT channels 2 and 3
+                       <2> - GPT channels 4 and 5
+                       <3> - GPT channels 6 and 7
+                       <4> - GPT channels 8 and 9
+                       <5> - GPT channels 10 and 11
+                       <6> - GPT channels 12 and 13
+                       <7> - GPT channels 14 and 15
+    description:
+      A list of phandle and channel index pair tuples to the POEGs that handle the
+      output disable for the GPT channels.
+
 required:
   - compatible
   - reg
@@ -375,4 +393,5 @@ examples:
         power-domains = <&cpg>;
         resets = <&cpg R9A07G044_GPT_RST_C>;
         #pwm-cells = <2>;
+        renesas,poegs = <&poeggd 4>;
     };
-- 
2.25.1




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