On 04/11/2022 10:27, Maxime Chevallier wrote:
> The Qualcomm IPQ4019 includes an internal 5 ports switch, which is
> connected to the CPU through the internal IPQESS Ethernet controller.
>
> Add support for this internal interface, which is internally connected to a
> modified version of the QCA8K Ethernet switch.
>
> This Ethernet controller only support a specific internal interface mode
> for connection to the switch.
>
> Signed-off-by: Maxime Chevallier <maxime.chevallier@xxxxxxxxxxx>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
> ---
> V6->V7:
> - No Changes
> V5->V6:
> - Removed extra blank lines
> - Put the status property last
> V4->V5:
> - Reword the commit log
> V3->V4:
> - No Changes
> V2->V3:
> - No Changes
> V1->V2:
> - Added clock and resets
>
> arch/arm/boot/dts/qcom-ipq4019.dtsi | 44 +++++++++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> index b23591110bd2..5fa1af147df9 100644
> --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
> +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
> @@ -38,6 +38,7 @@ aliases {
> spi1 = &blsp1_spi2;
> i2c0 = &blsp1_i2c3;
> i2c1 = &blsp1_i2c4;
> + ethernet0 = &gmac;
Hm, I have doubts about this one. Why alias is needed and why it is a
property of a SoC? Not every board has Ethernet enabled, so this looks
like board property.
I also wonder why do you need it at all?
Best regards,
Krzysztof
