> > > + - description: Main GMAC clock > > > + - description: Peripheral registers clock > > > + - description: Transmit SGMII clock > > > + - description: Transmit RGMII clock > > > + - description: Transmit RMII clock > > > + - description: Transmit MII clock > > > + - description: Receive SGMII clock > > > + - description: Receive RGMII clock > > > + - description: Receive RMII clock > > > + - description: Receive MII clock > > > + - description: > > > + PTP reference clock. This clock is used for programming the > > > + Timestamp Addend Register. If not passed then the system > > > + clock will be used. > Not clear to me has been whether the PHY mode can be switched at runtime > (like DPAA2 on Layerscape allows for SFPs) or whether this is fixed by board > design. Does the hardware support 1000BaseX? Often the hardware implementing SGMII can also do 1000BaseX, since SGMII is an extended/hacked up 1000BaseX. If you have an SFP connected to the SERDES, a fibre module will want 1000BaseX and a copper module will want SGMII. phylink will tell you what phy-mode you need to use depending on what module is in the socket. This however might be a mute point, since both of these are probably using the SGMII clocks. Of the other MII modes listed, it is very unlikely a runtime swap will occur. Andrew
