Hi Pierre >-----Original Message----- >From: Pierre Gondois [mailto:pierre.gondois@xxxxxxx] >Sent: Monday, October 31, 2022 2:50 PM >To: linux-kernel@xxxxxxxxxxxxxxx >Cc: pierre.gondois@xxxxxxx; Rob.Herring@xxxxxxx; Rob Herring ><robh+dt@xxxxxxxxxx>; Krzysztof Kozlowski ><krzysztof.kozlowski+dt@xxxxxxxxxx>; Alim Akhtar ><alim.akhtar@xxxxxxxxxxx>; devicetree@xxxxxxxxxxxxxxx; linux-arm- >kernel@xxxxxxxxxxxxxxxxxxx; linux-samsung-soc@xxxxxxxxxxxxxxx >Subject: [PATCH 06/20] arm64: dts: Update cache properties for exynos > >The DeviceTree Specification v0.3 specifies that the cache node 'compatible' >and 'cache-level' properties are 'required'. Cf. >s3.8 Multi-level and Shared Cache Nodes > Not sure if this need to be documented in schema/yaml file as well or already part of schema? >The recently added init_of_cache_level() function checks these properties. >Add them if missing. > >Signed-off-by: Pierre Gondois <pierre.gondois@xxxxxxx> >--- Changes looks good though. Reviewed-by: Alim Akhtar <alim.akhtar@xxxxxxxxxxx> > arch/arm64/boot/dts/exynos/exynos5433.dtsi | 2 ++ > arch/arm64/boot/dts/exynos/exynos7.dtsi | 1 + > 2 files changed, 3 insertions(+) > >diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi >b/arch/arm64/boot/dts/exynos/exynos5433.dtsi >index bd6a354b9cb5..e9eda46801f8 100644 >--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi >+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi >@@ -229,6 +229,7 @@ cluster_a57_l2: l2-cache0 { > cache-size = <0x200000>; > cache-line-size = <64>; > cache-sets = <2048>; >+ cache-level = <2>; > }; > > cluster_a53_l2: l2-cache1 { >@@ -236,6 +237,7 @@ cluster_a53_l2: l2-cache1 { > cache-size = <0x40000>; > cache-line-size = <64>; > cache-sets = <256>; >+ cache-level = <2>; > }; > }; > >diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi >b/arch/arm64/boot/dts/exynos/exynos7.dtsi >index 1cd771c90b47..aca1c32a6411 100644 >--- a/arch/arm64/boot/dts/exynos/exynos7.dtsi >+++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi >@@ -110,6 +110,7 @@ atlas_l2: l2-cache0 { > cache-size = <0x200000>; > cache-line-size = <64>; > cache-sets = <2048>; >+ cache-level = <2>; > }; > }; > >-- >2.25.1
