The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The recently added init_of_cache_level() function checks these properties. Add them if missing. Signed-off-by: Pierre Gondois <pierre.gondois@xxxxxxx> --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 2dd5e38820b1..c4bca23b96b9 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -52,6 +52,7 @@ cpu1: cpu@1 { }; L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; }; -- 2.25.1