The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The recently added init_of_cache_level() function checks
these properties. Add them if missing.
Signed-off-by: Pierre Gondois <pierre.gondois@xxxxxxx>
---
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 4 ++++
arch/arm64/boot/dts/apm/apm-storm.dtsi | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
index a8526f8157ec..68ba865fcd58 100644
--- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
@@ -97,15 +97,19 @@ cpu@301 {
};
xgene_L2_0: l2-cache-0 {
compatible = "cache";
+ cache-level = <2>;
};
xgene_L2_1: l2-cache-1 {
compatible = "cache";
+ cache-level = <2>;
};
xgene_L2_2: l2-cache-2 {
compatible = "cache";
+ cache-level = <2>;
};
xgene_L2_3: l2-cache-3 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi
index f56d687f772d..9ac7417f65eb 100644
--- a/arch/arm64/boot/dts/apm/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi
@@ -81,15 +81,19 @@ cpu@301 {
};
xgene_L2_0: l2-cache-0 {
compatible = "cache";
+ cache-level = <2>;
};
xgene_L2_1: l2-cache-1 {
compatible = "cache";
+ cache-level = <2>;
};
xgene_L2_2: l2-cache-2 {
compatible = "cache";
+ cache-level = <2>;
};
xgene_L2_3: l2-cache-3 {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
