This reverts commit e440e30e26dd6b0424002ad0ddcbbcea783efd85 because it
is not a reliable way of fixing SPI CS glitch and it depends on specific
Linux kernel pin controller driver behavior.
This behavior of kernel driver was changed in commit b991f8c3622c
("pinctrl: core: Handling pinmux and pinconf separately") thus
effectively the DTS fix stopped being effective.
Proper solution for the glitching SPI chip select must be implemented in
the drivers, not via ordering of entries in DTS, and is already
introduced in commit d21f4b7ffc22 ("pinctrl: qcom: Avoid glitching lines
when we first mux to output").
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
Reviewed-by: Douglas Anderson <dianders@xxxxxxxxxxxx>
Tested-by: Douglas Anderson <dianders@xxxxxxxxxxxx>
---
Changes since v3:
1. Add tags.
2. Update commig msg - mention pinctrl driver fix for glitch.
Changes since v2:
1. New patch
Not tested on hardware.
Cc: Doug Anderson <dianders@xxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 27 +++-----------------
1 file changed, 3 insertions(+), 24 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
index 1a1c346d619c..33817358ebb0 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
@@ -880,17 +880,17 @@ &sdhc_2 {
};
&spi0 {
- pinctrl-0 = <&qup_spi0_cs_gpio_init_high>, <&qup_spi0_cs_gpio>;
+ pinctrl-0 = <&qup_spi0_cs_gpio>;
cs-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
};
&spi6 {
- pinctrl-0 = <&qup_spi6_cs_gpio_init_high>, <&qup_spi6_cs_gpio>;
+ pinctrl-0 = <&qup_spi6_cs_gpio>;
cs-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>;
};
ap_spi_fp: &spi10 {
- pinctrl-0 = <&qup_spi10_cs_gpio_init_high>, <&qup_spi10_cs_gpio>;
+ pinctrl-0 = <&qup_spi10_cs_gpio>;
cs-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>;
cros_ec_fp: ec@0 {
@@ -1422,27 +1422,6 @@ pinconf {
};
};
- qup_spi0_cs_gpio_init_high: qup-spi0-cs-gpio-init-high {
- pinconf {
- pins = "gpio37";
- output-high;
- };
- };
-
- qup_spi6_cs_gpio_init_high: qup-spi6-cs-gpio-init-high {
- pinconf {
- pins = "gpio62";
- output-high;
- };
- };
-
- qup_spi10_cs_gpio_init_high: qup-spi10-cs-gpio-init-high {
- pinconf {
- pins = "gpio89";
- output-high;
- };
- };
-
qup_uart3_sleep: qup-uart3-sleep {
pinmux {
pins = "gpio38", "gpio39",
--
2.34.1
