On Wed, 19 Oct 2022 20:16:40 +0530, Thippeswamy Havalige wrote: > Convert to YAML schemas for Xilinx NWL PCIe Root Port Bridge > dt binding. > > Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@xxxxxxx> > --- > .../bindings/pci/xilinx-nwl-pcie.txt | 73 ----------- > .../bindings/pci/xilinx-nwl-pcie.yaml | 122 ++++++++++++++++++ > 2 files changed, 122 insertions(+), 73 deletions(-) > delete mode 100644 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt > create mode 100644 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.yaml > Running 'make dtbs_check' with the schema in this patch gives the following warnings. Consider if they are expected or the schema is incorrect. These may not be new warnings. Note that it is not yet a requirement to have 0 warnings for dtbs_check. This will change in the future. Full log is available here: https://patchwork.ozlabs.org/patch/ pcie@fd0e0000: Unevaluated properties are not allowed ('clocks', 'iommus', 'power-domains' were unexpected) arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dtb arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dtb arch/arm64/boot/dts/xilinx/zynqmp-smk-k26-revA.dtb arch/arm64/boot/dts/xilinx/zynqmp-zc1232-revA.dtb arch/arm64/boot/dts/xilinx/zynqmp-zc1254-revA.dtb arch/arm64/boot/dts/xilinx/zynqmp-zc1275-revA.dtb arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dtb arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dtb arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm017-dc3.dtb arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm018-dc4.dtb arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm019-dc5.dtb arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dtb arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dtb arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dtb arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dtb arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dtb arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dtb arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dtb arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dtb arch/arm64/boot/dts/xilinx/zynqmp-zcu111-revA.dtb
