On Wed, Oct 19, 2022 at 10:32:41AM -0400, Brian Masney wrote:
> On Mon, Oct 17, 2022 at 01:24:49PM +0200, Johan Hovold wrote:
> > + /*
> > + * Some Qualcomm platforms require interconnect bandwidth constraints
> > + * to be set before enabling interconnect clocks.
> > + *
> > + * Set an initial peak bandwidth corresponding to single-lane Gen 1
> > + * for the pcie-mem path.
> > + */
> > + ret = icc_set_bw(pcie->icc_mem, 0, MBps_to_icc(250));
>
> [snip]
>
> > + speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status);
> > + width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status);
> > +
> > + switch (speed) {
> > + case 1:
> > + bw = MBps_to_icc(250);
> > + break;
> > + case 2:
> > + bw = MBps_to_icc(500);
> > + break;
> > + default:
> > + case 3:
> > + bw = MBps_to_icc(985);
> > + break;
> > + }
>
> Just curious: These platforms have a 4 lane PCIe bus. Why use 985
> instead of 1000 for the maximum?
This is the per-lane bandwidth that depends on encoding. The four-lane
peak throughput would be about 3.94 GB/s.
Johan
