Hi Stephen,
> -----Original Message-----
> From: Jun Li <jun.li@xxxxxxx>
> Sent: Friday, September 30, 2022 10:54 PM
> To: sboyd@xxxxxxxxxx; abelvesa@xxxxxxxxxx
> Cc: robh+dt@xxxxxxxxxx; krzysztof.kozlowski+dt@xxxxxxxxxx;
> shawnguo@xxxxxxxxxx; s.hauer@xxxxxxxxxxxxxx; kernel@xxxxxxxxxxxxxx;
> festevam@xxxxxxxxx; dl-linux-imx <linux-imx@xxxxxxx>;
> mturquette@xxxxxxxxxxxx; l.stach@xxxxxxxxxxxxxx; Peng Fan
> <peng.fan@xxxxxxx>; alexander.stein@xxxxxxxxxxxxxxx;
> gregkh@xxxxxxxxxxxxxxxxxxx; devicetree@xxxxxxxxxxxxxxx;
> linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linux-clk@xxxxxxxxxxxxxxx
> Subject: [PATCH v4 2/3] clk: imx: imx8mp: add shared clk gate for usb suspend
> clk
>
> 32K usb suspend clock gate is shared with usb_root_clk, this shared clock
> gate was initially defined only for usb suspend clock, usb suspend clk is
> kept on while system is active or system sleep with usb wakeup enabled, so
> usb root clock is fine with this situation; with the commit cf7f3f4fa9e5
> ("clk: imx8mp: fix usb_root_clk parent"), this clock gate is changed to be
> for usb root clock, but usb root clock will be off while usb is suspended,
> so usb suspend clock will be gated too, this cause some usb functionalities
> will not work, so define this clock to be a shared clock gate to conform
> with the real HW status.
>
> Fixes: 9c140d9926761 ("clk: imx: Add support for i.MX8MP clock driver")
> Cc: stable@xxxxxxxxxxxxxxx # v5.19+
> Tested-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx>
> Signed-off-by: Li Jun <jun.li@xxxxxxx>
Is this version okay for you?
Thanks
Li Jun
> ---
> change for v4:
> - improve the commit log to explain why this is stable stuff.
>
> drivers/clk/imx/clk-imx8mp.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index e89db568f5a8..5b66514bdd0c 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -17,6 +17,7 @@
>
> static u32 share_count_nand;
> static u32 share_count_media;
> +static u32 share_count_usb;
>
> static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy",
> "dummy", }; static const char * const audio_pll1_bypass_sels[] =
> {"audio_pll1", "audio_pll1_ref_sel", }; @@ -673,7 +674,8 @@ static int
> imx8mp_clocks_probe(struct platform_device *pdev)
> hws[IMX8MP_CLK_UART2_ROOT] = imx_clk_hw_gate4("uart2_root_clk",
> "uart2", ccm_base + 0x44a0, 0);
> hws[IMX8MP_CLK_UART3_ROOT] = imx_clk_hw_gate4("uart3_root_clk",
> "uart3", ccm_base + 0x44b0, 0);
> hws[IMX8MP_CLK_UART4_ROOT] = imx_clk_hw_gate4("uart4_root_clk",
> "uart4", ccm_base + 0x44c0, 0);
> - hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate4("usb_root_clk",
> "hsio_axi", ccm_base + 0x44d0, 0);
> + hws[IMX8MP_CLK_USB_ROOT] = imx_clk_hw_gate2_shared2("usb_root_clk",
> "hsio_axi", ccm_base + 0x44d0, 0, &share_count_usb);
> + hws[IMX8MP_CLK_USB_SUSP] =
> imx_clk_hw_gate2_shared2("usb_suspend_clk",
> +"osc_32k", ccm_base + 0x44d0, 0, &share_count_usb);
> hws[IMX8MP_CLK_USB_PHY_ROOT] = imx_clk_hw_gate4("usb_phy_root_clk",
> "usb_phy_ref", ccm_base + 0x44f0, 0);
> hws[IMX8MP_CLK_USDHC1_ROOT] = imx_clk_hw_gate4("usdhc1_root_clk",
> "usdhc1", ccm_base + 0x4510, 0);
> hws[IMX8MP_CLK_USDHC2_ROOT] = imx_clk_hw_gate4("usdhc2_root_clk",
> "usdhc2", ccm_base + 0x4520, 0);
> --
> 2.34.1
