Hi,
On Mon, Sep 19, 2022 at 11:44:51AM +0200, Johan Hovold wrote:
> The USB0 SS PHY node had the PCS_MISC register block (0x1200) replaced
> with PCS_USB (0x1700).
>
> Fixes: 152d1faf1e2f ("arm64: dts: qcom: add SC8280XP platform")
> Signed-off-by: Johan Hovold <johan+linaro@xxxxxxxxxx>
Reviewed-by: Andrew Halaney <ahalaney@xxxxxxxxxx>
Thanks for the patch, I think this patch makes sense from what I'm
seeing of upstream's expectations (that register space should be
PCS_MISC's) downstream, register names, and offsets.
Being verbose because it took me a little bit to figure out, but here's
the offset and registers I found downstream which correlate to
your change:
/* Module: USB3_PCS_MISC_USB3_PCS_MISC_USB3_PCS_MISC */
#define USB3_PCS_MISC_TYPEC_CTRL 0x1200
#define USB3_PCS_MISC_TYPEC_PWRDN_CTRL 0x1204
#define USB3_PCS_MISC_PCS_MISC_CONFIG1 0x1208
#define USB3_PCS_MISC_CLAMP_ENABLE 0x120C
#define USB3_PCS_MISC_TYPEC_STATUS 0x1210
#define USB3_PCS_MISC_PLACEHOLDER_STATUS 0x1214
Your description of the PCS_USB region accidentally being used in the
prior version also adds up with what I see.
Thanks,
Andrew
> ---
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 49ea8b5612fc..e8905445ca19 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -1184,7 +1184,7 @@ usb_0_ssphy: usb3-phy@88eb400 {
> <0 0x088ec400 0 0x1f0>,
> <0 0x088eba00 0 0x100>,
> <0 0x088ebc00 0 0x3ec>,
> - <0 0x088ec700 0 0x64>;
> + <0 0x088ec200 0 0x18>;
> #phy-cells = <0>;
> #clock-cells = <0>;
> clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> --
> 2.35.1
>
